• Journal of Korean Society of Industrial and Systems Engineering
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• v.46 no.2
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• pp.1-12
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• 2023

To make semiconductor chips, a number of complex semiconductor manufacturing processes are required. Semiconductor chips that have undergone complex processes are subjected to EDS(Electrical Die Sorting) tests to check product quality, and a wafer bin map reflecting the information about the normal and defective chips is created. Defective chips found in the wafer bin map form various patterns, which are called defective patterns, and the defective patterns are a very important clue in determining the cause of defects in the process and design of semiconductors. Therefore, it is desired to automatically and quickly detect defective patterns in the field, and various methods have been proposed to detect defective patterns. Existing methods have considered simple, complex, and new defect patterns, but they had the disadvantage of being unable to provide field engineers the evidence of classification results through deep learning. It is necessary to supplement this and provide detailed information on the size, location, and patterns of the defects. In this paper, we propose an anomaly detection framework that can be explained through FCDD(Fully Convolutional Data Description) trained only with normal data to provide field engineers with details such as detection results of abnormal defect patterns, defect size, and location of defect patterns on wafer bin map. The results are analyzed using open dataset, providing prominent results of the proposed anomaly detection framework.

• Journal of the Semiconductor & Display Technology
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• v.12 no.2
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• pp.57-61
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• 2013

This paper presents adaptive neuro-fuzzy inference based defect detection method for various defect types, such as micro-crack, fingerprint and contamination, in heterogeneously textured surface of polycrystalline solar wafers. Polycrystalline solar wafer consists of various crystals so the surface of solar wafer shows heterogeneously textures. Because of this property the visual inspection of defects is very difficult. In the proposed method, we use local binary feature and fuzzy reasoning for defect detection. Experimental results show that our proposed method achieves a detection rate of 80%~100%, a missing rate of 0%~20% and an over detection (overkill) rate of 9%~21%.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Korean Journal of Materials Research
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• v.32 no.9
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• pp.396-402
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• 2022

In this study, surface roughness and interfacial defect characteristics were analyzed after forming a high-k oxide film on the surface of a prime wafer and a test wafer, to study the possibility of improving the quality of the test wafer. As a result of checking the roughness, the deviation in the test after raising the oxide film was 0.1 nm, which was twice as large as that of the Prime. As a result of current-voltage analysis, Prime after PMA was 1.07 × 10 A/cm² and Test was 5.61 × 10 A/cm², which was about 5 times lower than Prime. As a result of analyzing the defects inside the oxide film using the capacitance-voltage characteristic, before PMA Prime showed a higher electrical defect of 0.85 × 10¹² cm^-2 in slow state density and 0.41 × 10¹³ cm^-2 in fixed oxide charge. However, after PMA, it was confirmed that Prime had a lower defect of 4.79 × 10¹¹ cm^-2 in slow state density and 1.33 × 10¹² cm^-2 in fixed oxide charge. The above results confirm the difference in surface roughness and defects between the Test and Prime wafer.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.05a
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• pp.42-45
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• 2002

General wheel mark in mono-crystalline silicon wafer finding is able to be expected because it depends on radius ratio and angular velocity ratio of wafer and wheel. The pattern is predominantly determined by the contour of abrasive grits resulting from a relative motion. Although such a wheel mark is made uniform pattern if the process parameters are fixed, sub-surface defect is expected to be distributed non-uniformly because of characteristic of mono-crystalline silicon wafer that has diamond cubic crystal. Consequently it is considered that this phenomenon affects the following process. This paper focused on kinematic analysis of wafer grinding process and simulation program was developed to verify the effect of process variables on wheel mark. And finally, we were able to predict sub-surface defect distribution that considered characteristic of mono-crystalline silicon wafer

• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.81-86
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• 2023

Recently, there has been an increased demand for light-emitting diode (LED) due to the growing emphasis on environmental protection. However, the use of GaN-based sapphire in LED manufacturing leads to the generation of defects, such as dislocations caused by lattice mismatch, which ultimately reduces the luminous efficiency of LEDs. Moreover, most inspections for LED semiconductors focus on evaluating the luminous efficiency after packaging. To address these challenges, this paper aims to detect defects at the wafer stage, which could potentially improve the manufacturing process and reduce costs. To achieve this, image processing and deep learning-based defect detection techniques for Sapphire Epi-Wafer used in Green LED manufacturing were developed and compared. Through performance evaluation of each algorithm, it was found that the deep learning approach outperformed the image processing approach in terms of detection accuracy and efficiency.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1510-1512
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• 2000

Due to the shrinking of the chip size and increasing of the complexity in the modern electronic devices. the defect of wafer are so important to decide the yield in the device process. The engineers has studied the wafer defects and the characteristics. They published lots of the experimental methods. I did an experiment the gettering effect of the defects due to the high temperature and the long time diffusion. Actually, As the thickness of the wafer backside polysilicon is thicker and the diffusion time is faster. the defects on the wafer are decreased. The polysilicon gram boundaries of the wafer backside played an important part as the defect gettering site.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.10a
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• pp.241-242
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• 2012

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.729-730
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• 2010

• Current Photovoltaic Research
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• v.5 no.2
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• pp.59-62
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• 2017

Surface texturing is affected the uniformity and size of pyramid with saw mark defect density. To analysis the influence of the saw mark defect density, we textured various si wafer. When the texturing process proceeds without the saw mark removal, silicon wafer of low-saw mark defect density showed small pyramid size of $3.5{\mu}m$ with the lowest average value of the reflectance of 10.6%. When texturing carried out after removal of the saw mark using the TMAH solution, we obtained a reflectance of about 11% and the large pyramid size of $5{\mu}m$. As a result, saw mark wafers showed a better pyramid structure than saw mark-free wafer. This result showed that saw mark can take place more smooth etching by the KOH solution and saw mark-free wafer is determined to be a factor that have a higher reflectance and a large pyramid.