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http://dx.doi.org/10.3740/MRSK.2022.32.9.396

Surface Defect Properties of Prime, Test-Grade Silicon Wafers  

Oh, Seung-Hwan (Department of Energy Engineering, Dankook University)
Yim, Hyeonmin (Department of Energy Engineering, Dankook University)
Lee, Donghee (Department of Energy Engineering, Dankook University)
Seo, Dong Hyeok (Department of Energy Engineering, Dankook University)
Kim, Won Jin (Department of Energy Engineering, Dankook University)
Kim, Ryun Na (Department of Energy Engineering, Dankook University)
Kim, Woo-Byoung (Department of Energy Engineering, Dankook University)
Publication Information
Korean Journal of Materials Research / v.32, no.9, 2022 , pp. 396-402 More about this Journal
Abstract
In this study, surface roughness and interfacial defect characteristics were analyzed after forming a high-k oxide film on the surface of a prime wafer and a test wafer, to study the possibility of improving the quality of the test wafer. As a result of checking the roughness, the deviation in the test after raising the oxide film was 0.1 nm, which was twice as large as that of the Prime. As a result of current-voltage analysis, Prime after PMA was 1.07 × 10 A/cm2 and Test was 5.61 × 10 A/cm2, which was about 5 times lower than Prime. As a result of analyzing the defects inside the oxide film using the capacitance-voltage characteristic, before PMA Prime showed a higher electrical defect of 0.85 × 1012 cm-2 in slow state density and 0.41 × 1013 cm-2 in fixed oxide charge. However, after PMA, it was confirmed that Prime had a lower defect of 4.79 × 1011 cm-2 in slow state density and 1.33 × 1012 cm-2 in fixed oxide charge. The above results confirm the difference in surface roughness and defects between the Test and Prime wafer.
Keywords
prime Si wafer; test Si wafer; wafer grades; surface defect; surface roughness;
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