• 반도체디스플레이기술학회지
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• 제9권1호
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• pp.11-16
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• 2010

Wafer Pre-Alignment is to find the center and the orientation of a wafer and to move the wafer to the desired position and orientation. In this paper, an area camera based pre-aligning method is presented that captures 8 wafer images regularly during 360 degrees rotation. From the images, wafer edge positions are extracted and used to estimate the wafer's center and orientation using least squares circle fitting. These data are utilized for the proper alignment of the wafer. For accurate alignments, camera calibration methods using high order polynomials are used for converting pixel coordinates into real-world coordinates. A complete pre-alignment system was constructed using mechanical and optical components and tested. Experimental results show that alignment of wafer center and orientation can be done with the standard deviation of 0.002 mm and 0.028 degree, respectively.

• 반도체디스플레이기술학회지
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• 제9권3호
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• pp.47-51
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• 2010

This paper presents a wafer pre-alignment system which is improved using the image of the entire wafer area. In the previous method, image acquisition for wafer takes about 80% of total pre-alignment time. The proposed system uses only one image of entire wafer area via a high-resolution CMOS camera, and so image acquisition accounts for nearly 1% of total process time. The larger FOV(field of view) to use the image of the entire wafer area worsen camera lens distortion. A camera calibration using high order polynomials is used for accurate lens distortion correction. And template matching is used to find a correct notch's position. The performance of the proposed system was demonstrated by experiments of wafer center alignment and notch alignment.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2009년도 추계학술대회
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• pp.410-413
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• 2009

웨이퍼 Pre-Alignment는 반도체 공정에서 장비에 웨이퍼를 놓기 전에 웨이퍼의 중심 및 방향을 정확하게 정렬할 필요가 있는데, 이를 위해서 일정한 수준 이하로 중심과 방향을 찾아 Alignment 하는 방법을 말한다. 본 논문에서는 웨이퍼를 Alignment 하기 위해 기존의 Mechanical한 방법이 아닌 Area 카메라를 통한 비접촉식 방법을 이용하였다. 이 방법은 웨이퍼를 45도씩 8번씩, 한 바퀴를 회전하여 이미지를 획득한 뒤, 이미지의 웨이퍼의 에지값 들을 이용하여 Least Square Circle Fitting을 이용하여 웨이퍼의 중심과 방향을 정확하게 측정하여 Alignment를 한다.

• 제어로봇시스템학회논문지
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• 제8권9호
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• pp.812-817
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• 2002

This paper presents a development of high accuracy aligner and describes a method to find the orientation of a substantially circular disk shaped wafer with at least one flat region on an edge thereof. In the developed system, the wafer is spun one 360 degree turn on a chuck and the edge position is measured by a linear array to obtain a set of data points at various wafer orientation. The rotation axis may differ from wafer center by an unknown eccentricity. The flat angle is found by fitting a cosine curve to the actual data to obtain a deviation. The maximum deviation is then corrected for errors due to a finite number of data points and wafer eccentricity by calculating an adjustment angle from data points on the wafer fiat. After determining the flat angle the wafer is spun to the desired orientation. The wafer eccentricity can be calculated from four of the data points located away from the flat edge region. and the wafer is then centered.

• 한국정밀공학회지
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• 제31권10호
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.108-112
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• 2023

Precision manufacturing technology is rapidly developing due to the extreme miniaturization of semiconductor processes to comply with Moore's Law. Accurate and precise alignment, which is one of the key elements of the semiconductor pre-process and post-process, is very important in the semiconductor process. The center detection of wafer align marks plays a key role in improving yield by reducing defects and research on accurate detection methods for this is necessary. Methods for accurate alignment using traditional image sensors can cause problems due to changes in image brightness and noise. To solve this problem, engineers must go directly into the line and perform maintenance work. This paper emphasizes that the development of AI technology can provide innovative solutions in the semiconductor process as high-resolution image and image processing technology also develops. This study proposes a new wafer center detection method through variable thresholding. And this study introduces a method for detecting the center that is less sensitive to the brightness of LEDs by utilizing a high-performance object detection model such as YOLOv8 without relying on existing algorithms. Through this, we aim to enable precise wafer focus detection using artificial intelligence.

• 분석과학
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• 제13권2호
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• pp.222-228
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• 2000

비분산 적외선 방식에 의한 대기 중 일산화 탄소 측정용 검출기를 제작하고, 감도 및 안정성을 조사하였다. 검출 감도를 향상시키기 위하여 동일 흡수셀 내에 3개의 반사거울을 장착하여 셀 안에서의 빛의 통과거리가 증가되도록 설계하였다. 50cm 길이의 셀 안에서 빛의 통과거리를 16m까지 늘릴 수 있도록 컴퓨터 모사에 의해 반사거울의 곡률반경 및 곡률중심, 셀 안에서의 위치 등을 산출하여 셀을 제작하였다. 빛의 경로와 광학적 특성은 모의 셀 안에서 laser beam alignment에 의해 확인하였다. 투과광의 검출에는 광전도성 PbSe센서를 사용하였으며, 센서소자는 열전냉각방식에 의해 냉각하였다. 제작된 일산화 탄소 검출기의 검출한계와 스팬 드리프트는 각각 0.24ppm과 0.03ppm(v/v)이었다.

• 방사선산업학회지
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• 제8권3호
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• pp.147-153
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• 2014

This paper describes a large area CMOS image sensor module Implementation using the precision align inspection program. This work is needed because wafer cutting system does not always have high precision. The program check more than 8 point of sensor edges and align sensors with moving table. The size of a $2{\times}1$ butted CMOS image sensor module which except for the size of PCB is $170mm{\times}170mm$. And the pixel size is $55{\mu}m{\times}55{\mu}m$ and the number of pixels is $3,072{\times}3,072$. The gap between the two CMOS image sensor module was arranged in less than one pixel size.

• Transactions on Electrical and Electronic Materials
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• 제14권2호
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• pp.63-66
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• 2013

This paper describes the highly productive process technologies of microprobe arrays, which were used for a probe card to test a Dynamic Random Access Memory (DRAM) chip with fine pitch pads. Cantilever-type microprobe arrays were fabricated using conventional micro-electro-mechanical system (MEMS) process technologies. Bonding material, gold-tin (Au-Sn) paste, was used to bond the Ni-Co alloy microprobes to the ceramic space transformer. The electrical and mechanical characteristics of a probe card with fabricated microprobes were measured by a conventional probe card tester. A probe card assembled with the fabricated microprobes showed good x-y alignment and planarity errors within ${\pm}5{\mu}m$ and ${\pm}10{\mu}m$, respectively. In addition, the average leakage current and contact resistance were approximately 1.04 nA and 0.054 ohm, respectively. The proposed highly productive microprobes can be applied to a MEMS probe card, to test a DRAM chip with fine pitch pads.