• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.399-399
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• 2013

Metal silicides는 Si 기반의microelectronic devices의 interconnect와 contact 물질 등에 사용하기 위하여 그 형성 mechanism과 전기적 특성에 대한 연구가 많이 이루어지고 있다. 이 중 Rare-earth(RE) silicides는 저온에서 silicides를 형성하고, n-type Si과 낮은 Schottky Barrier contact (~0.3 eV)을 이룬다. 또한 낮은 resistivity와 Si과의 작은 lattice mismatch, 그리고 epitaxial growth의 가능성, 높은 thermal stability 등의 장점을 갖고 있다. RE silicides 중 ytterbium silicide는 가장 낮은 electric work function을 갖고 있어 n-channel schottky barrier MOSFETs의 source/drain으로 주목받고 있다. 또한 Silicon 기반의 CMOSFETs의 성능 향상 한계로 인하여 germanium 기반의 소자에 대한 연구가 이루어져 왔다. Ge 기반 FETs 제작을 위해서는 낮은 source/drain series/contact resistances의 contact을 형성해야 한다. 본 연구에서는 저접촉 저항 contact material로서 ytterbium germanide의 가능성에 대해 고찰하고자 하였다. HRTEM과 EDS를 이용하여 ytterbium germanide의 미세구조 분석과 면저항 및 Schottky Barrier Heights 등의 전기적 특성 분석을 진행하였다. Low doped n-type Ge (100) wafer를 1%의 hydrofluoric (HF) acid solution에 세정하여 native oxide layer를 제거하고, 고진공에서 RF sputtering 법을 이용하여 ytterbium 30 nm를 먼저 증착하고, 그 위에 ytterbium의 oxidation을 방지하기 위한 capping layer로 100 nm 두께의 TiN을 증착하였다. 증착 후, rapid thermal anneal (RTA)을 이용하여 N2 분위기에서 $300{\sim}700^{\circ}C$에서 각각 1분간 열처리하여 ytterbium germanides를 형성하였다. Ytterbium germanide의 미세구조 분석은 transmission electron microscopy (JEM-2100F)을 이용하였다. 면 저항 측정을 위해 sulfuric acid와 hydrogen peroxide solution (H2SO4:H2O2=6:1)에서 strip을 진행하여 TiN과 unreacted Yb을 제거하였고, 4-point probe를 통하여 측정하였다. Yb germanides의 면저항은 열처리 온도 증가에 따라 감소하다 증가하는 경향을 보이고, $400{\sim}500^{\circ}C$에서 가장 작은 면저항을 나타내었다. HRTEM 분석 결과, deposition 과정에서 Yb과 Si의 intermixing이 일어나 amorphous layer가 존재하였고, 열처리 온도가 증가하면서 diffusion이 더 활발히 일어나 amorphous layer의 두께가 증가하였다. $350^{\circ}C$ 열처리 샘플에서 germanide/Ge interface에서 epitaxial 구조의 crystalline Yb germanide가 형성되었고, EDS 측정 및 diffraction pattern을 통하여 안정상인 YbGe2-X phase임을 확인하였다. 이러한 epitaxial growth는 면저항의 감소를 가져왔으며, 열처리 온도가 증가하면서 epitaxial layer가 증가하다가 고온에서 polycrystalline 구조의 Yb germanide가 형성되어 면저항의 증가를 가져왔다. Schottky Barrier Heights 측정 결과 또한 면저항 경향과 동일하게 열처리 증가에 따라 감소하다가 고온에서 다시 증가하였다.

• Journal of Sensor Science and Technology
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• v.10 no.3
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• pp.148-155
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• 2001

A pressure sensor on the tip of a catheter which is utilized to measure the in-vivo pressure in a human body was fabricated and the characteristic of the pressure sensor as measured. To fit into a catheter with 1 mm caliber, samples of $150\;{\mu}m$(thickness) ${\times}$ (600, 700, 800, 900, 1000) ${\mu}m$(width) ${\times}2\;mm$(length) was fabricated. The thicker face with $450\;{\mu}m$ thickness of SDB wafer was made thin to $134\;{\mu}m$ thickness using KOH etchant and it made possible to fabricate sensor cell with the width shorter than 1 mm. Different to the whitstone bridge sensor, we formed one piezoresistor and one reference resistor in sensor. Therefore there are possibilities of reduction of the sensitivity, then by using the simulation tool ANSYS 5.5.1, the location and the type of the piezoresistor was optimized. Another piezoresistor type of sensor which contain one longitudinal and one transverse piezoresistor was fabricated at the same time, but the sensitivity was not improved very much. To get the output versus the pressure, a constant current source and a implementation amplifier was used. As a result, the maximum sensitivity of the sensor with one piezoresistor was $1.6\;{\mu}V/V/mmHg$.

• Journal of Astronomy and Space Sciences
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• v.21 no.4
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• pp.481-492
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• 2004

We report the successful fabrication and I-V curve superconductivity test results of the Nb/Al-based superconducting tunnel junctions. STJs with side-lengths of 20, 40, 60 and $80{\mu}m$ were fabricated by deposition of polycrystalline Nb/Al/AlOx/Al/Nb 5-layer thin films incorporated on a 3-inch Si wafer. STJ was designed by $Tanner^{TM}$ L-Edit 8.3 program, and fabricated in SQUID fabrication facility, KRISS. S-layer STJ thin-films were fabricated using UV photolithography, DC magnetron sputtering, Reactive ion etching, and CVD(Chemical Vapor Deposition) techniques. Superconducting state test for STJ was succeeded in 4K with liquid helium cooling system. Their performance indicators such ie energy gap, normal resistance, normal resistivity, dynamic resistance, dynamic resistivity, and quality factor were measured from I-V curve. Fabricated Nb/Al STJ shows $11\%$ higher FWHM energy resolution than genuine Nb STJ.

• Journal of Powder Materials
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• v.22 no.5
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• pp.321-325
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• 2015

The triboelectric property of a material is important to improve an efficiency of triboelectric generator (TEG) in energy harvesting from an ambient energy. In this study, we have studied the TEG property of a semiconducting $SnO_2$ which has yet to be explored so far. As a counter triboelectric material, PET and glass are used. Vertical contact mode is utilized to evaluate the TEG efficiency. $SnO_2$ thin film is deposited by atomic layer deposition on bare Si wafer for various thicknesses from 5.2 nm to 34.6 nm, where the TEG output is increased from 13.9V to 73.5V. Triboelectric series are determined by comparing the polarity of output voltage of 2 samples among $SnO_2$, PET, and glass. In conclusion, $SnO_2$, as an intrinsic n-type material, has the most strong tendency to be positive side to lose the electron and PET has the most strong tendency to be negative side to get the electron, and glass to be between them. Therefore, the $SnO_2$-PET combination shows the highest TEG efficiency.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.1
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• pp.603-608
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• 2018

Although the voltage-applied discharge method is most widely used in the semiconductor and display industries, periodic management costs are incurred because the method causes defects due to the absorption of ambient fine dust and causes emitter tip contamination due to the discharge. The emitter tip contamination problem is caused by the accumulation of fine particles in ambient air due to the corona discharge of the ionizer. Fuzzy ball generation accelerates the wear of the emitter tip and deteriorates the performance of the ionizer. Although a mechanical cleaning method using a manual brush or an automatic brush is effective for contaminant removal, it requires management of additional mechanical parts by the user. In some cases, contaminants accumulated in the emitter may be transferred to the wafer or product. In order to solve this problem, we developed an ionizer for a clean environment that can remove the pencil-type emitter tip and directly ionize the surrounding gas molecules using the tungsten wire located inside the ion tank. As a result of testing and certification by the Korea Institute of Machinery and Materials, the average concentration was $0.7572particles/ft^3$, the decay time was less than two seconds, and the ion valance was 7.6 V, which is satisfactory.

• Resources Recycling
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• v.22 no.2
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• pp.22-28
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• 2013

In the present study, the possibility of recovering and recycling the silicon carbide(SiC) from a silicon sludge by removing Fe and Si impurities was investigated. Si and SiC were separated from the silicon sludge using centrifugation. The separated SiC concentrate consisted of Fe, Si and SiC, in which Fe and Si were removed to recover the pure SiC. Leaching with acid/alkali solution was compared with the vapor-phase chlorination. The Fe concentration removed in the SiC was 49 ppm, and it was separated by leaching with 1 M HCl solution at $80^{\circ}C$ for 1 h. The Si concentration removed in the SiC was 860 ppm, and it was separated by leaching with 1M NaOH solution at $50^{\circ}C$ for 1 h. The SiC concentrate was chlorinated in a tubular reactor, 2.4 cm in diameter and 32 cm in length. The boat filled with SiC concentrate was located at the midpoint of the alumina tube, then, the chlorine and nitrogen gas mixture was introduced. The Fe and Si concentration removed in the SiC were 48 ppm and 405 ppm, respectively, at $500^{\circ}C$ reactor temperature, 4 h reaction time, 300 cc/min gas flow rate, and 10% $Cl_2$ gas mole fraction.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.80-89
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• 2006

The rapid development of process technology and the introduction of new materials not only make it difficult for process control but also as a result increase process variations. These process variations are barriers to successful implementation of design circuits because there are disparities between data on layout and that on wafer. This paper proposes a new design environment to determine the interconnect worstcase with accuracy and speed so that the interconnect effects due to process-induced variations can be applied to designs of $0.13{\mu}m$ and below. Common Geometry and Maximum Probability methods have been developed and integrated into the new worstcase optimization algorithm. The delay time of the 31-stage Ring Oscillator, manufactured in UMC $0.13{\mu}m$ Logic, was measured, and the results proved the accuracy of the algorithm. When the algorithm was used to optimize worstcase determination, the relative error was less than 1.00%, two times more accurate than the conventional methods. Furthermore, the new worstcase design environment improved optimization speed by 32.01% compared to that of conventional worstcase optimizers. Moreover, the new worstcitse design environment accurately predicted the worstcase of non-normal distribution which conventional methods cannot do well.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.33-38
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• 2001

We investigate the via-size dependance of as-electroplated- and reflow-bump shapes for realizing both high-density and high-aspect ratio of solder bump. The solder bump is fabricated by subsequent processes as follows. After sputtering a TiW/Al electrode on a 5-inch Si-wafer, a thick photoresist for via formation it obtained by multiple-codling method and then vias with various diameters are defined by a conventional photolithography technique using a contact alinger with an I-line source. After via formation the under ball metallurgy (UBM) structure with Ti-adhesion and Cu-seed layers is sputtered on a sample. Cu-layer and Sn/pb-layer with a competition ratio of 6 to 4 are electroplated by a selective electroplating method. The reflow-bump diameters at bottom are unchanged, compared with as-electroplated diameters. As-electroplated- and reflow-bump shapes, however, depend significantly on the via size. The heights of as-electroplated and reflow bumps increase with the larger cia, while the aspect ratio of bump decreases. The nearest bumps may be touched by decreasing the bump pitch in order to obtain high-density bump. The touching between the nearest bumps occurs during the overplating procedure rather than the reflowing procedure because the mushroom diameter formed by overplating is larger than the reflow-bump diameter. The arrangement as zig-zag rows can be effective for realizing the flip-chip-interconnect bump with both high-density and high-aspect ratio.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.49-53
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• 2011

High-speed Cu filling into a through-silicon-via (TSV) and simplification of bumping process by electroplating for three dimensional stacking of Si dice were investigated. The TSV was prepared on a Si wafer by deep reactive ion etching, and $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to increase the filling rate of Cu into the via, a periodic-pulse-reverse wave current was applied to the Si chip during electroplating. In the bumping process, Sn-3.5Ag bumping was performed on the Cu plugs without lithography process. After electroplating, the cross sections of the vias and appearance of the bumps were observed by using a field emission scanning electron microscope. As a result, voids in the Cu-plugs were produced by via blocking around via opening and at the middle of the via when the vias were plated for 60 min at -9.66 $mA/cm^2$ and -7.71 $mA/cm^2$, respectively. The Cu plug with a void or a defect led to the production of imperfect Sn-Ag bump which was formed on the Cu-plug.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.65-74
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• 2013

The through-silicon via (TSV) technology is essential for 3-dimensional integrated packaging. TSV technology, however, is still facing several reliability issues including interfacial delamination, crack generation and Cu protrusion. These reliability issues are attributed to themo-mechanical stress mainly caused by a large CTE mismatch between Cu via and surrounding Si. In this study, the thermo-mechanical reliability of copper TSV technology is investigated using numerical analysis. Finite element analysis (FEA) was conducted to analyze three dimensional distribution of the thermal stress and strain near the TSV and the silicon wafer. Several parametric studies were conducted, including the effect of via diameter, via-to-via spacing, and via density on TSV stress. In addition, effects of annealing temperature and via size on Cu protrusion were analyzed. To improve the reliability of the Cu TSV, small diameter via and less via density with proper via-to-via spacing were desirable. To reduce Cu protrusion, smaller via and lower fabrication temperature were recommended. These simulation results will help to understand the thermo-mechanical reliability issues, and provide the design guideline of TSV structure.