• 반도체디스플레이기술학회지
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• 제19권3호
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• pp.55-60
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• 2020

The hard mask photo-resist strip inspection system for the semiconductor wafer manufacturing process inspects the position of the circuit pattern formed on the wafer by measuring the distance from the edge of the wafer to the strip processing area. After that, it is an inspection system that enables you to check the process status in real time. Process defects can be significantly reduced by applying a tester that has not been applied to the existing wafer strip process, edge etching process, and wafer ashing process. In addition, it is a technology for localizing semiconductor process inspection equipment that can analyze the outer diameter of the wafer and the state of pattern formation, which can secure process stability and improve wafer edge yield.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2005년도 추계학술대회 논문집
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• pp.427-431
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• 2005

In this study, 6' GaAs wafer bonding system is designed and optimized to bond 6 inches device wafer and material wafer. Bonding process is performed in vacuum environment and resin is used to bond two wafers. Vacuum module and double heating mechanisms are adopted to minimize wafer warpage and void. Structure and heat transfer analysis, et al of the core modules review the designed mechanisms are very effective in performance improvement. As a result, high productivity (tack time cut-down) and stabilized process can be obtained by reducing breakage failure of wafer.

• 산업기술연구
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• 제43권1호
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• pp.49-55
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• 2023

Cluster tools are extensively employed in various wafer fabrication processes within the semiconductor manufacturing industry, including photo lithography, etching, and chemical vapor deposition. Contemporary fabrication facilities encounter customer orders with technical specifications that are similar yet slightly varied. Consequently, modern fabrications concurrently manufacture two or three different wafer types using a cluster tool to maximize chamber utilization and streamline the flow of wafer lots between different process stages. In this review, we introduce two methods of concurrent processing of multiple wafer types: 1) concurrent processing of multiple wafer types with different job flows, 2) concurrent processing of multiple wafer types with identical job flows. We describe relevant research trends and achievements and discuss future research directions.

• 대한산업공학회지
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• 제29권2호
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• pp.179-189
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• 2003

Gate poly-silicon critical dimension is a prime characteristic of a metal-oxide-semiconductor field effect transistor. It is important to achieve the uniformity of gate poly-silicon critical dimension in order that a semiconductor device has acceptable electrical test characteristics as well as a semiconductor wafer fabrication process has a competitive net-die-per-wafer yield. However, on gate poly-silicon critical dimension, the complexity associated with a semiconductor wafer fabrication process entails hierarchical variance components according to run-to-run, wafer-to-wafer and even die-to-die production unit changes. Specifically, estimates of the hierarchical variance components are required not only for disclosing dominant sources of the variation but also for testing the wafer-level uniformity. In this paper, two experimental designs, a two-stage nested design and a randomized complete block design are considered in order to estimate the hierarchical variance components. Since gate poly-silicon critical dimensions are collected from fixed die positions within wafers, a factor representing die positions can be regarded as fixed in linear statistical models for the designs. In this context, the two-stage nested design also checks the wafer-level uniformity taking all sampled runs into account. In more detail, using variance estimates derived from randomized complete block designs, Duncan's multiple range test examines the wafer-level uniformity for each run. Consequently, a framework presented in this study could provide guidelines to practitioners on estimating the hierarchical variance components and testing the wafer-level uniformity in parallel for any characteristics concerned in semiconductor wafer fabrication processes. Statistical analysis is illustrated for an experimental dataset from a real pilot semiconductor wafer fabrication process.

• 한국재료학회지
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• 제24권12호
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• pp.682-688
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• 2014

Physical and chemical changes in a polished wafer and in $2.5{\mu}m$ & $4{\mu}m$ epitaxially grown Si layer wafers (Epilayer wafer) after surface treatment were investigated. We characterized the influence of surface treatment on wafer properties such as surface roughness and the chemical composition and bonds. After each surface treatment, the physical change of the wafer surface was evaluated by atomic force microscopy to confirm the surface morphology and roughness. In addition, chemical changes in the wafer surface were studied by X-ray photoemission spectroscopy measurement. Changes in the chemical composition were confirmed before and after the surface treatment. By combined analysis of the physical and chemical changes, we found that diluted hydrofluoric acid treatment is more effective than buffered oxide etching for $SiO_2$ removal in both polished and Epi-Layer wafers; however, the etch rate and the surface roughness in the given treatment are different among the polished $2.5{\mu}m$ and $4{\mu}m$ Epi-layer wafers in spite of the identical bulk structural properties of these wafers. This study therefore suggests that independent surface treatment optimization is required for each wafer type, $2.5{\mu}m$ and $4{\mu}m$, due to the meaningful differences in the initial surface chemical and physical properties.

• 한국기계가공학회지
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• 제19권3호
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• pp.22-28
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• 2020

This paper investigates the effects of retaining ring materials, particularly PPS and PEEK, used in the CMP process, on wafer polishing and ring wear. CMP can be performed using bonded type retaining rings made with PPS or injection molding type retaining rings made with PEEK. In this study, after polishing a wafer with a PPS retaining ring, the average profile height of the wafer was 0.098 ㎛ less than that of the wafer polished with a PEEK retaining ring, implying that PPS retaining rings achieve a higher polishing rate. In addition, the center area of the wafer profile had less deviation and improved flatness after polishing with the PPS ring. These results indicate that a higher polishing rate and smaller profile height deviation can be achieved using retaining rings made with PPS compared to retaining rings made with PEEK. Therefore, with semiconductor circuit patterns becoming finer and wafer sizes becoming larger, the use of PPS in CMP retaining rings can obtain more stable wafer polishing results compared to that of PEEK.

• 마이크로전자및패키징학회지
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• 제20권1호
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• pp.1-5
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• 2013

3D integration 기술 특히 W2W integration 기술은 전자산업의 디바이스 scaling 문제를 해결하고 고성능화 소형화 추세에 맞춘 가장 핵심적인 기술 방향이다. 그러나 W2W integration 기술은 현재 가격과 생산수율의 장애를 가지고 있고, 이를 해결하기 위해서 웨이퍼 매칭, 리던던시, 다이 면적 축소, 배선 층 수 축소와 같은 디자인 연구들이 진행되고 있다. W2W integration 기술이 대량생산으로 연결되기 위해서는 우선적으로 웨이퍼 본딩, 실리콘연삭, TSV 배선 공정의 최적화가 이루어져야 하겠지만, 가격을 포함한 생산수율을 높이기 위해서는 반드시 디자인 연구가 선행되어야 하겠다.

• 조명전기설비학회논문지
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• 제22권6호
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• pp.148-155
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• 2008

본 논문에서는 웨이퍼 에지 노광장비에 핵심 부분인 웨이퍼의 편심오차의 측정알고리즘과 플랫/노치의 방향을 해석하는 알고리즘을 제안하였다. 또한 새로 제안된 알고리즘을 전산 시뮬레이션을 통해 그 유효성을 확인하였으며 제작된 웨이퍼 에지 노광기에 적용하여 실제 장비에 적용 가능함을 확인하였다. 제안된 알고리즘을 위해 필요한 웨이퍼 에지 위치 검출방식에 있어 과거의 접촉식 방법을 사용함으로서 발생하는 파티클의 오염을 제거하기 위해 선형 CCD 센서를 적용한 비접촉 방식의 데이터 측정법을 적용함으로서 파티클의 오염을 제어 할 수 있었다.

• 반도체디스플레이기술학회지
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• 제16권3호
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• pp.1-7
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• 2017

Multi-wafer planetary type chemical vapor deposition reactors are widely used in thin film growth and suitable for large scale production because of the high degree of growth rate uniformity and process reproducibility. In this study, a two-dimensional model for estimating the effect of the gap between satellite and wafer on the wafer surface temperature distribution is developed and analyzed using computational fluid dynamics technique. The simulation results are compared with the results obtained from an analytical method. The simulation results show that a drop in the temperature is noticed in the center of the wafer, the temperature difference between the center and wafer edges is about $5{\sim}7^{\circ}C$ for all different ranges of the gap, and the temperature of the wafer surface decreases when the size of the gap increases. The simulation results show a good agreement with the analytical ones which is based on one-dimensional heat conduction model.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.629-632
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• 1998

This paper presents a new and simple technique to realize high Q inductor on low resistivity silicon wafer with 6 $\Omega$.cm. This technique is very compatible with bipolar and CMOS standard silicon process. By forming the deep and narrow trenches on the low resistivity wafer substrate under inductor pattern, oxidizing and filling with undoped polysilicon, the low resistivity silicon wafer acts as high resistivity wafer being suitable for the fabrication of high Q inductor. By using this technique the quality factor (Q) for 8-turn spiral inductor was improved up to max. 10.3 at 2 ㎓ with 3.0 $\mu\textrm{m}$ of metal thickness. The experiment results show that Q on low resistivity silicon wafer with the trench technique have been improved more than 2 times compared to the conventional low resistivity silicon wafer without trenches.