• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.118-129
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• 2010

A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.61-67
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• 2006

We developed a constant current source which is insensitive to threshold voltage variation caused by irregular grain boundary distribution in polycrystalline silicon. The proposed current source has superior saturation characteristics over wide range of input voltages as well as small current error compared to the previously reported Vth compensated sources. We measured the circuit performance and error in current due to parameter variation by using HSPICE.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1172-1175
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• 2007

We have investigated the threshold voltage shifts(${\Delta}Vth$) and drain current level shift (${\Delta}Ids$) in subthreshold region of a-Si:H TFTs induced by DC Bias (Vgs and Vds) - Temperature stress (BTS) condition. We plotted the transfer curves and the ${\Delta}Vth$ contour maps as Vds-Vds stress bias and Temperature to examine the severe damage cases on TFTs. Also, by drawing out the time-dependent transfer curve (Ids-Vgs) in the region of $10^{-8}\;{\sim}\;10^{-13}$ (A) current level, we can estimate the failure time of TFTs in a operating condition.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.97-98
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• 2006

For high performance transistor in the 0.14um generation, high speed sram is using a weak region of SCE(Short Channel Effect). It causes serious SCE problem (Vth Roll-Off and Punch-Through etc). This paper shows improvement of Vth roll-off and Ion/Ioff characteristics through high concentration Pocket implant, LDD(Light Dopped Dram) and low energy Implant to reduce S/D Extension resistance. We achieve stabilized Vth and Improved transistor Ion/Ioff performance of 10%.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.403-404
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• 2012

We fabricated TFT devices with the GeSe channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is high. Based on the experiments, we draw the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.08a
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• pp.280-281
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• 2011

We fabricated the devices of TFT type with the amorphous chalcogenide channel. A single device consists of a Pt source and drain, a Ti glue layer and a GeSe chalcogenide channel layer on SiO2/Si substrate which worked as the gate. We confirmed the drain current with variations of gate bias and channel size. The I-V curves of the switching device are shown in Fig. 1. The channel of the device always contains amorphous state, but can be programmed into two states with different threshold voltages (Vth). In each state, the device shows a normal Ovonic switching behavior. Below Vth (OFF state), the current is low, but once the biasing voltage is greater than Vth (ON state), the current increases dramatically and the ON-OFF ratio is about 4 order. Based on the experiments, we contained the conclusion that the gate voltage can enhance the drain current, and the electric field by the drain voltage affects the amorphous-amorphous transition. The switching device always contains the amorphous state and never exhibits the Ohmic behavior of the crystalline state.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.167.2-167.2
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• 2015

고 이동도(~10 cm/Vs), 낮은 공정온도 및 높은 투과율 등의 특성을 갖는 산화물 반도체는 저 소비전력, 대면적화 및 고해상도 LCD Panel에 적합한 재료로서 현재 일부 Mobile Panel 및 TFT-LCD Panel의 양산에 적용되고 있으나, 향후 UHD급(4 K, 8 K)의 대형, 고해상도 Panel에의 적용을 위해서는 30 cm2/Vs 이상의 고 이동도 재료의 개발 및 저 저항 배선의 적용에 따른 소자 신뢰성의 개선이 필요하다. Cu는 대표적인 저 저항 배선 재료로 일부 양산에 적용되고 있으나, Cu 전극과 산화물 반도체의 계면에서 Cu원자의 확산 및 Cu-O 층의 형성에 의한 소자 특성 저하의 문제가 있다. 본 연구에서는 고 이동도의 In doped-ZTO계 산화물 반도체를 기반으로 채널 층과 Cu source-Drain layer의 계면에서의 Cu element의 거동 및 TFT 소자 특성과의 상관관계를 고찰하고, 계면에 형성된 Cu-O layer에 대해 높은 전자 친화도를 갖는 Ca element를 첨가에 의한 TFT 소자 특성의 변화를 관찰하였다. 본 연구에서는 이러한 효과로 인한 소자 신뢰성의 향상을 기대하였으며, 우선 In doped-ZTO 채널 층에 Cu와 CuCa 2at% source-drain을 적용한 TFT 특성을 확인하였다. 그 결과, Cu는 Field-effect mobility: ~17.67 cm2/Vs, Sub-threshold swing: 0.76 mV/decade 및 Vth:, 4.40 V의 결과가 얻어졌으며 CuCa 2at%의 경우 Field-effect mobility: ~17.84 cm2/Vs, Sub-threshold swing: 0.86 mV/decade 및 Vth:, 5.74 V의 결과가 얻어졌다. 소자신뢰성 측면에서도 Bias Stress의 변화량 ${\delta}Vth$의 경우 Cu : 4.48 V에 대해 CuCa 2at% : 2.81 V로 ${\delta}Vth$:1.67 V의 개선된 결과를 얻었다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.3
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• pp.25-31
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• 1977

Fe V spinels were prepared by sintering the well-ground stoichiometric mixtures of Fe O and V O at 1,10$0^{\circ}C$ under H -CO atmosphere. The activation energy for electrical conduction decreases with increasing amount of iron. The tendency of activation energy depending on the amount of iron contained clarifies that the electrical condction of the spinel is mainly due to electron hopping between Fe and Fe ions at B sites. In the experiment for negative resistance characteristics, the threshold voltage (Vth) for the samples is related to ambient temperature, thickness and raising rate of applied voltage. Vth decreases as temperature increases while Vth increases linearly with thickness and Vth increases linearly with the raising rate of applied voltage in semi-logarithmic scale. These results lead to a conclusion that current paths mainly formed by thermal breakdown are ascribed to the negative resistance phenomena. Applying this property, these vanadium iron spinels may be used for switching elements.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.485-488
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• 2004

As scaling down the cell channel length, the increment of B concentration in channel region is inevitable to overcome the punch-through, especially in flash memory cell with 90nm technology. This paper shows that the high dose ion implantation in channel cause the Si defect. which has been proved to be the major cause of the tailed Vth in distribution. And also mechanical stress due to SiN-anneal process can induce the Si dislocation. and get worse it. With decreasing the channel implantation dose, skipping the anneal and reducing the mechanical stress, Si defect problem is solved completely. We are verify first that the optimization of B concentration in channel must be certainly considered in order to improve Si defect. It is also certainly necessary to stabilize the distribution of cell Vth in the next generation of flash memory.

• Proceedings of the Korean Vacuum Society Conference
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• 2015.08a
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• pp.209.1-209.1
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• 2015

Indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) 그리고 zinc tin oxide (ZTO) 같은 zinc oxide 기반의 산화물 반도체는 높은 이동도, 투과도 그리고 유연성 같은 장점을 갖고 있어, display application의 backplane 소자로 적용되고 있다. 또한 최근에는 산화물 반도체를 이용한 thin-film transistor (TFT) 뿐만아니라 resistive random access memory (RRAM), flash memory 그리고 pH 센서 등 다양한 반도체 소자에 적용을 위한 연구가 활발히 진행 중이다. 그러나 zinc oxide 기반의 산화물 반도체의 전기 화학적 불안정성은 위와 같은 소자에 적용하는데 제약이 있다. 산화물 반도체의 안정성에 영향을 미치는 다양한 요인들 중 한 가지는, sputter 같은 plasma를 이용한 공정 진행 시 active layer가 plasma에 노출되면서 threshold voltage (Vth)가 급격하게 변화하는 plasma damage effect 이다. 급격한 Vth의 변화는 동작 전압의 불안정성을 가져옴과 동시에 누설전류를 증가시키는 결과를 초래 한다. 따라서 본 연구에서는, IGZO 기반의 TFT를 제작 후 plasma 분위기에 노출시켜, power와 노출 시간에 따른 전기적 특성 변화를 확인 하였다. 또한, thermal annealing을 적용하여 열처리 온도와 시간에 따른 Vth의 회복특성을 조사 하였다. 이러한 결과는 추후 산화물 반도체를 이용한 다양한 소자 설계 시 유용할 것으로 기대된다.