• Journal of Power Electronics
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• 제16권1호
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• pp.388-397
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• 2016

An error-compensated pulse width modulator (ECPWM) is proposed to improve the baseband harmonic performance and the switching loss of voltage source inverters (VSIs). Selecting between harmonic distortion and switching loss is a design tradeoff in the conventional space vector pulse width modulation. In this work, an accumulated difference in produced and desired phase voltages is considered to adjust the reference signal. This mechanism can compensate for the voltage error in the previous carrier period. With error compensation every half-carrier period, the proposed ECPWM allows one-half reduction in carrier frequency without scarifying baseband harmonic distortion. The proposed modulator is applied to a three-phase VSI with R-L load and a motor-speed-control system for experiments. The measured efficiency and operating temperature of switches confirm the effectiveness of the proposed scheme.

• 대한전기학회논문지:전력기술부문A
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• 제50권8호
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• pp.373-378
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• 2001

This paper introduces a new online index to quantify the harmonic distortion. The proposed index based on VI product can represent the harmonic distortion of both voltage and current, and it includes the effect of interharmonic distortion. Also, the new index is suitable to online harmonic distortion evaluation since it only requires the r.m.s. (root mean square) value and fundamental frequency value of the signals. Case studies are presented to show the availability of the proposed index using the comparison with the THD (Total Harmonic Distortion).

• Journal of Electrical Engineering and Technology
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• 제10권1호
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• pp.30-40
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• 2015

For a shunt power quality controller (SPQC) the DC side voltage value which is closely related to the compensation performance is a significant parameter. Buy so far, very little discussion has been conducted on this in a quantitative manner by previous publications. In this paper, a method to design the DC side voltage of SPQC is presented according to the compensation performance in the single-phase system and the three-phase system respectively. First, for the reactive current and the harmonic current compensation, a required minimal value of the DC side voltage with a zero total harmonic distortion (THD) of the source current and a unit power factor is obtained for a typical load, through the equivalent circuit analysis and the Fourier Transform analytical expressions. Second, when the DC side voltage of SPQC is lower than the above-obtained minimal value, the quantitative relationship between the DC side voltage and the THD after compensation is also elaborated using the curve diagram. Hardware experimental results verify the design method.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1328-1336
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• 2013

Nowadays multilevel inverters are developing generally due to reduced voltage stress on power switches and low total harmonic distortion (THD) in output voltage. However, for increasing the output voltage levels the number of circuit devices are increased and it results in increasing the cost of converter. In this paper, a novel multilevel inverter is proposed. The suggested topology uses less number of power switches and related gate drive circuits to generate the same level in output voltage with comparison to traditional cascaded multilevel inverter. With the proposed topology all levels in output voltage can be realized. As an illustration, a symmetric 13-level and asymmetric 29-level proposed inverters have been simulated and implemented. The total peak inverse (PIV) and power losses of presented inverter are calculated and compared with conventional cascaded multilevel inverter. The presented analyses show that the power losses in the suggested multilevel inverter are less than the traditional inverters. Presented simulation and experimental results demonstrate the feasibility and applicability of the proposed inverter to obtain the maximum number of levels with less number of switches.

• Journal of Electrical Engineering and Technology
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• 제12권1호
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• pp.100-109
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• 2017

This paper proposes performance improvement schemes for sensorless PMSM control drive using a four-switch three-phase inverter (so-called B4 inverter). In the proposed scheme, the back-EMF estimation-based sensorless control algorithm is used to control the brushless PMSM without position sensors. In order to have stable operation, this paper presents a gain adjustment scheme that compensates the reduction of stable sensorless operation range as long as the rotor speed increases. In B4 topology, the center point of dc-link capacitors is connected to 3-phase load, and it is prone to have the load current distortion. Hence, to mitigate this problem, a distortion compensation scheme by modifying voltage commands using measured dc-link potentials is proposed in this paper. The validity of the proposed method is evaluated by simulations and experiments.

• 대한전자공학회논문지TC
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• 제37권8호
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• pp.45-51
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• 2000

본 논문에서는 지수형, 삼각형 및 체비쉐브 테이퍼 전송선로에서 디지털 펄스가 전송될 때 분산과 반사에 의해 나타나는 펄스의 왜곡 특성을 시간영역에서 해석하여 그 전송특성을 비교하여 나타내었다. 그리고 테이퍼 선로에서 전압과 전류의 전달함수를 구하여 상승과 하강 시간을 갖는 비이상형 구형 펄스를 입력했을 때 왜곡 특성을 해석하고, 선로에서 나타나는 분산과 반사가 파형의 왜곡에 미치는 영향을 분석하였다. 주파수 분산에 의한 왜곡은 파형에 오버슈트와 기울림이 나타났고, 반사에 의한 왜곡은 꼬리 부분에 잔류 특성이 나타났다.

• Journal of Power Electronics
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• 제16권6호
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• pp.2258-2271
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• 2016

In this paper, some crucial performance characteristics related to the operational reliability of the post-fault Pulse Width Modulated (PWM) rectifiers, such as line current harmonic distortion, Common Mode Voltage (CMV), and current stress on the capacitors, are fully investigated. The aforementioned performance characteristics of post-fault rectifiers are highly dependent on the utilized space vector modulation (SVM) schemes, which are also examined. Detailed analyses of the three most commonly used SVM schemes for post-fault PWM rectifiers are provided, revealing the major differences in terms of the zero vector synthesis approaches. To compare the performances of the three SVM schemes, the operating principles of a post-fault rectifier are presented with various SVM schemes. Using analytical and numerical methods in the time domain, the performances of the line current distortion, common mode voltage and capacitor current are evaluated and compared for each SVM scheme. The proposed analysis demonstrates that the zero vector synthesis approaches of the considered methods have significant impacts on the performance characteristics of rectifiers. In addition, the advantages and disadvantages of the proposed SVM schemes are discussed. The experimental results verify the effectiveness and validity of the proposed analysis.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(1)
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• pp.271-274
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• 2000

In this paper, the distortion of an electrical pulse with rise/fall time resulting from dispersion and reflection as it propagates along a tapered microstrip line is investigated, and the delay time and distortion rate with respect to input and load impedances are analyzed on triangular and exponential tapered lines and analyzed the influence of the reflection and frequency dispersion on the distorted voltage wave in the tapered lines. The observed overshoot in front of the distorted wave is caused due to the frequency dispersion and the sustained tail of that comes from the reflection in the tapered line.

• ETRI Journal
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• 제29권6호
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• pp.835-837
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• 2007

A multi-bit sigma-delta modulator architecture is described for low-distortion performance and a high-speed operation. The proposed architecture uses both a delayed code and a delayed differential code of analog-to-digital converter in the feedback path, thereby suppressing signal components in the integrators and relaxing the timing requirement of the analog-to-digital converter and the scrambler logic. Implemented by a 0.13 ${\mu}m$ CMOS process, the sigma-delta modulator achieves high linearity. The measured spurious-free dynamic range is 89.1 dB for -6 dBFS input signal.

• 한국산학기술학회논문지
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• 제13권12호
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• pp.6052-6059
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• 2012

본 논문에서는 전산실 파워라인의 고조파 문제를 다룬다. 전산실 UPS의 부하 측 각 상의 전압 및 전류는 한국전력공사 전기공급 약관의 규제치 전압 왜형률 5%와 전류 왜형률 5%, 그리고 KS C 4310 의 무정전 전원장치인 UPS의 출력측 고조파 전류 한도 5% 이하를 만족시켜야 한다. 그러나 측정 결과 전압 왜형률은 0.86%로 한국전력공사 규제치에 부합하나, 전류 왜형률은 34.98%로 한국전력공사 규제치인 5%를 초과하여 부적합하였다. 이에 대한 대책으로 AC필터를 설치한 결과 전류 왜형률이 15.22%로, 기준 값 이내에는 미치지 못하였으나 본래의 34.98%에서 절반에 가까운 수준에는 근접 하는 효과가 있었다.