• Proceedings of the KIEE Conference
• /
• 1999.07f
• /
• pp.2804-2806
• /
• 1999

This paper presents a voltage regulator for an AC power supply. It is designed to have the band Pass filter characteristic for the system to be free from DC-offset or sub-frequency fluctuation in the output voltage wave

• The Transactions of the Korean Institute of Electrical Engineers P
• /
• v.64 no.3
• /
• pp.143-145
• /
• 2015

One of the many problems besetting the converter designer is being able to design a switching power supply that can operate in the range of very wide input voltage. Specially, in an emergency diesel generator system, the AVR(Automatic Voltage Regulator) is a regulator which regulates the output voltage of the generator at a nominal constant voltage level. In addition, the AVR must be operated in very wide input voltage. Therefore, a power supply for the AVR must be operated at the very wide input voltage range. In this paper, a quasi-resonant flyback power supply with very wide input voltage range is proposed. Also, the performance of the proposed power supply is demonstrated through experiments.

• Journal of Electrical Engineering and Technology
• /
• v.12 no.1
• /
• pp.11-18
• /
• 2017

In order to maintain customer voltages within the allowable limit($220{\pm}13V$) as much as possible, tap operation strategy of SVR(Step Voltage Regulator) which is located in primary feeder, is widely used for voltage control in the utilities. However, SVR in nature has operation characteristic of the delay time ranging from 30 to 150 sec, and then the compensation of BESS (Battery Energy Storage System) during the delay time is being required because the customer voltages in distribution system may violate the allowable limit during the delay time of SVR. Furthermore, interconnection of PV(Photovoltaic) system could make a difficultly to keep customer voltage within the allowable limit. Therefore, this paper presents an optimal coordination operation algorithm between BESS and SVR based on a conventional LDC (Line Drop Compensation) method which is decided by stochastic approach. Through the modeling of SVR and BESS using the PSCAD/EMTDC, it is confirmed that customer voltages in distribution system can be maintained within the allowable limit.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.12 no.6
• /
• pp.2698-2706
• /
• 2011

This paper deals with the optimal operation algorithm of SVR(Step Voltage Regulator) which is located with primary feeders and proposes the optimal operation system to evaluate customer voltage. The existing algorithm of SVR adapts the constant sending voltage method, which may cause the power quality problems such as overvoltage and under voltage variations in case where the distributed generations are interconnected with the primary feeders. Therefore, this paper proposes the optimal algorithm of LDC method for SVR using least square method to obtain the optimal setting values. Also, this paper presents the optimal evaluation system based on the former algorithm. The simulation results according to the types and capacities of distributed generations shows the effectiveness.

• Journal of Power Electronics
• /
• v.14 no.2
• /
• pp.217-225
• /
• 2014

This paper deals with the optimization of the driving techniques for the ZVT synchronous buck converter proposed in [1]. Two new gate drive circuits are proposed to allow this converter to operate by only one control signal as a 12V voltage regulator module (VRM). Voltage-driven method is applied for the synchronous rectifier. In addition, the control signal drives the main and auxiliary switches by one driving circuit. Both of the circuits are supplied by the input voltage. As a result, no supply voltage is required. This approach decreases both the complexity and cost in converter hardware implementation and is suitable for practical applications. In addition, the proposed SR driving scheme can also be used for many high frequency resonant converters and some high frequency discontinuous current mode PWM circuits. The ZVT synchronous buck converter with new gate drive circuits is analyzed and the presented experimental results confirm the theoretical analysis.

• Journal of IKEEE
• /
• v.25 no.1
• /
• pp.201-205
• /
• 2021

In this paper present Low Drop-Out (LDO) regulator that improved load transient characteristics due to the push-pull detection structure. The response characteristic of the voltage delta value is improved due to the proposed push-pull sensing circuit structure between the input terminal of the LDO regulator pass transistor and the output terminal of the internal error amplifier. Voltage value has improved load transient characteristics than conventional LDO regulator. Compared to the conventional LDO regulator, it has an improved response speed of approximately 244 ns at rising time and approximately 90 ns at falling time. The proposed circuit was simulated by the samsung 0.13um process using Cadence's Specter and Virtuoso simulator.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.4
• /
• pp.263-271
• /
• 2013

A low dropout regulator (LDO) with fast transient responses is presented. The proposed LDO eliminates the trade-off between slew rate and unity gain bandwidth, which are the key parameters for fast transient responses. In the proposed buffer, by changing the slew current path, the slew rate and unity gain bandwidth can be controlled independently. Implemented in $0.18-{\mu}m$ high voltage CMOS, the proposed LDO shows up to 200 mA load current with 0.2 V dropout voltage for $1{\mu}F$ output capacitance. The measured maximum transient output voltage variation, minimum quiescent current at no load condition, and maximum unity gain frequency are 24 mV, $7.5{\mu}A$, and higher than 1 MHz, respectively.

• Proceedings of the KIEE Conference
• /
• 2001.07a
• /
• pp.149-151
• /
• 2001

This paper proposes the design of STATCOM(static synchronous compensator) stabilizer for improving power system stability using fuzzy logic controller(FLC). The STATCOM DC voltage regulator contributes negative damping to the power system as the installation of STATCOM DC voltage regulator. STATCOM stabiliser is superimposed on the AC voltage regulator to compensate the negative damping effect. To evaluate usefulness of the proposed method, we perform the nonlinear simulation on a single-machine infinite bus system. As results of the simulations, the proposed method shows better control performance than PI controller in terms of damping effects.

• Proceedings of the KIEE Conference
• /
• 1994.07a
• /
• pp.310-312
• /
• 1994

A partial shunt regulator (PSR) which is the power regulator of KOREASAT is modeled. The modeling of the PSR consist of solar array, power circuit, controller. and load models. To realize simple structure. a voltage source of the PSR controller is used the output voltage of the PSR. The model of the PSR has very complex structure with two additional coupled feedback loops. The complex model is simplified to a simple meaningful model with only main feedback control loop. The proposed model is compared to a PSR model with DC voltage source at the PSR controller. The proposed PSR model is verified by comparing the model with SPICE simulation for small signal analysis.

• ETRI Journal
• /
• v.42 no.5
• /
• pp.790-798
• /
• 2020

Herein, a low-ripple coarse-fine digital low-dropout regulator (D-LDO) without ringing in the transient state is proposed. Conventional D-LDO suffers from a ringing problem when settling the output voltage at a large load transition, which increases the settling time. The proposed D-LDO removes the ringing and reduces the settling time using an auxiliary power stage which adjusts its output current to a load current in the transient state. It also achieves a low output ripple voltage using a comparator with a complete comparison signal. The proposed D-LDO was fabricated using a 65-nm CMOS process with an area of 0.0056 μ㎡. The undershoot and overshoot were 47 mV and 23 mV, respectively, when the load current was changed from 10 mA to 100 mA within an edge time of 20 ns. The settling time decreased from 2.1 ㎲ to 130 ns and the ripple voltage was 3 mV with a quiescent current of 75 ㎂.