• 한국정보통신학회논문지
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• 제16권8호
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• pp.1741-1746
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• 2012

본 논문에서는 기존의 Dickson's charge pump에 개선된 배전압 회로를 조합하여 구성된 고전압 출력에 용이한 전압 증배기 회로를 소개한다. 기존의 charge pump로 얻어진 전압을 승압에 다시 사용하는 구조로 배전압기를 응용하여 전압 증배를 가속화 하면서도 DMOS의 구조적 신뢰성을 저하하지 않도록 회로 구조를 제안하였다. 제안된전압증배기는 3V 입력 전원의 6단 회로 구성으로 약 33V의 출력을 내며 6단 이상의 구성으로 고전압 증배도 가능하다. 제안된 회로의 성능을 평가하기 위해 Magna DMOS 공정을 이용하여 시뮬레이션 하였으며 이론적인 증배와 일치함을 보였여 최소한의 소자 사용으로 고전압 전압 증배가 가능한 새로운 전압 증배기를 제시하였다.

• 반도체디스플레이기술학회지
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• 제16권2호
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• pp.85-88
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• 2017

In this paper, we have designed and fabricated a RF-DC voltage multiplier for 5.8GHz microwave wireless power transmission. In order to obtain higher voltage, the RF-DC voltage multiplier with 10 diodes (D-10) and the receiver module with an antenna and BPF (Band Pass Filter) was manufactured. The measured and compared results show that the voltages of the proposed one are lower than those of the previous tripler module up to 40cm. However, the voltage of the proposed one with the voltage multiplier is higher than that of the tripler module at the distances of 45cm and 50cm due to the voltage multiplier with 10 diodes.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.301-304
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• 2001

The analog multiplier is very useful building block in many circuits such as filter, frequency-shifter, and modulators. In recent year, The main design issue of circuit designer is low-voltage/low-power system design, because of all systems are recommended very integrated system and portable system In this paper, the proposed the four-quadrant analog multiplier is using the bulk-driven techniques. The bulk-driven technique is very useful technique in low-voltage system, compare with gate-driven technique. therefore the proposed analog multiplier is operated in 1V supply voltage. And the proposed analog multiplier is low power dissipation compare with the others. therefor the proposed analog multiplier is convenient in low-voltage/low-power in system.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.238-241
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• 1999

Analog-to-digital converter has attracted a lot of interests as one of the most prospective area of an application of Josephson Junction technology. Recently, the development of a digital-to-analog converter has been pursued to achieved the high performance. One of the main advantage in using single flux quantum logic in a digital-to-analog converter is the low voltage drop in a single Josephson Junction and hence the resolution of the output voltage of this digital-to-analog converter can be very high. In this work, we have used a software, called WRspice, to study a voltage multiplier circuit which is the basic block in building a digital-to-analog circuit. In simulation, we operated a voltage multiplier with .4 Josephson Junctions per stage and studied the dependence on the circuit bias currents and the circuit inductors of the voltage multiplier. Our simulation results showed a fast operation and reasonable circuit margins.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.244-247
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• 1999

In this paper, a low voltage CMOS analog four-quadrant multiplier is presented. The proposed multiplier is composed of a pair of transconductor and lowers supply voltage down to $V_{T}$+2 $V_{Ds,sat}$+ $V_{DS,triode}$. The designed analog four-quadrant multiplier have simulated by HSPICE using 0.25${\mu}{\textrm}{m}$ n-well CMOS process with a 1.2V supply voltage. Simulation results show that the THD can be 1.28% at maximum differential input of 0.7 $V_{p-p}$././.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.587-590
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• 2005

We investigated the input impedance characteristics of UHF-band RFID tag chip for increased reading range. A voltage multiplier designed using 0.4 ${\mu}m$ $zero-V_T$ MOSFET showed that DC output voltage of 2 V can be obtained using standard CMOS process. The input impedance of the voltage multiplier was examined to achieve impedance level for maximum reading distance using analytical and numerical approaches. The input impedance of the voltage multiplier could be varied in a wide range by selecting the size of MOSFET and the number of multiplying stages of the voltage multiplier, and thus, the impedance level required for the tag antenna can be obtained in presence of other tag circuit blocks.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 춘계학술대회
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• pp.696-698
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• 2012

본 논문에서는 기존의 Dickson's charge pump에 개선된 배전압 회로를 조합하여 구성된 새로운 전압증배기 회로를 소개한다. 기존의 charge pump로 얻어진 전압을 승압에 다시 사용하는 구조로 배전압기를 응용하여 전압증배를 가속화 하면서도 DMOS의 구조적 신뢰성을 저하하지 않도록 회로 구조를 제안하였다. 제안된 6단 전압증배기는 3V 전원으로 약 33V의 출력을 내며 6단 이상의 구성으로 고전압 증배도 가능하다. 제안된 회로의 성능을 평가하기 위해 Magna DMOS 공정을 이용하여 시뮬레이션 하였으며 이론적인 증배와 일치함을 보였여 최소한의 소자 사용으로 고전압 전압증배가 가능한 새로운 전압증배기를 제시하였다.

• 반도체디스플레이기술학회지
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• 제20권2호
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• pp.29-33
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• 2021

A 5.8-GHz 1W wireless power transmission system was used for charging a smart phone. The voltage of one RF power receiver with antenna was not enough for charging. Several power receivers for charging a smart phone was connected serially. The voltage of several RF power receivers are highly enough for charging a smart phone within 50cm. However, the lack of current from small capacitances of RF-DC converters is not suitable for charging smart phone. It means very long charging time. In this paper, the voltage multiplier circuits for RF-DC converters were analyzed to increase the current and voltage at the same time to reduce the charging time in smartphone RF wireless charging. Through the analysis of multiplier circuits, the 7-stage parallel multiplier circuit with voltage-doubler units are suitable for charging the smartphone, which supplies 5V and 700mA at 3V@5.8GHz.

• 정보처리학회논문지A
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• 제14A권4호
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• pp.203-208
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• 2007

본 논문에서는 CMOS 다치 논리회로를 이용하여 $64{\times}64$ 비트 Modified Booth 곱셈기를 설계하였다. 설계한 곱셈기는 Radix-4 알고리즘을 이용하여 전류모드 CMOS 4치 논리회로로 구현하였다. 이 곱셈기는 트랜지스터 수를 기존의 전압모드 2진 논리 곱셈기에 비해 64.4% 감소하였으며, 내부 구조를 규칙적으로 배열하여 확장성을 갖도록 설계하였다. 설계한 회로는 2.5V의 공급전압과 단위전류 $5{\mu}A$를 사용하여, $0.25{\mu}m$ CMOS 기술을 이용하여 구현하였으며 HSPICE를 사용하여 검증하였다. 시뮬레이션 결과, 2진 논리 곱셈기는 $7.5{\times}9.4mm^2$의 점유면적에 9.8ns의 최대 전달지연시간과 45.2mW의 평균 전력소모 특성을 갖는 반면, 설계한 곱셈기는 $5.2{\times}7.8mm^2$의 점유면적에 11.9ns의 최대 전달지연시간과 49.7mW의 평균 전력소모 특성으로 점유면적이 42.5% 감소하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.646-649
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• 2002

In this paper, a low-voltage CMOS squarer and a four-quadrant analog multiplier are presented. It is based on a source-coupled pair and a scaled-floating voltage generator which are modified to work as a voltage squaring and a sum/difference circuits. The proposed squarer/multiplier have been simulated with HSPICE, where -3㏈ bandwidth of 10MHz is achieved. The power consumption is about 0.6㎽, from a ${\pm}$1.5V supply, and the total harmonic distortion is less than 0.7%, with a 1.2V peak-to-peak 1MHz input signal.