• Journal of international Conference on Electrical Machines and Systems
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• 제2권2호
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• pp.197-201
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• 2013

Cascaded H-bridge multilevel inverter requires independent DC voltage sources to produce multi output voltage levels. When it needs to generate more levels in the output voltage wave, the number of independent DC voltage sources usually limits its extension. To solve this problem, we propose a cascaded H-bridge multilevel inverter employing a front-end flyback converter for unifying input DC voltage sources. After theoretical analysis of the proposed circuit, we verify the validity of the proposed inverter using computer-aided simulations and experiments.

• ETRI Journal
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• 제35권5호
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• pp.797-807
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• 2013

In this paper, an input receiver with a hysteresis characteristic that can work at voltage levels between 0.9 V and 5 V is proposed. The input receiver can be used as a wide voltage range Schmitt trigger also. At the same time, reliable circuit operation is ensured. According to the research findings, this is the first time a wide voltage range Schmitt trigger is being reported. The proposed circuit is compared with previously reported input receivers, and it is shown that the circuit has better noise immunity. The proposed input receiver ends the need for a separate Schmitt trigger and input buffer. The frequency of operation is also higher than that of the previously reported receiver. The circuit is simulated using HSPICE at 0.35-${\mu}m$ standard thin oxide technology. Monte Carlo analysis is conducted at different process conditions, showing that the proposed circuit works well for different process conditions at different voltage levels of operation. A noise impulse of ($V_{CC}/2$) magnitude is added to the input voltage to show that the receiver receives the correct logic level even in the presence of noise. Here, $V_{CC}$ is the fixed voltage supply of 3.3 V.

• Journal of Power Electronics
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• 제10권2호
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• pp.155-164
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• 2010

This paper presents a voltage control algorithm for a hybrid multilevel inverter based on a staged-perception of the inverter voltage vector diagram. The algorithm is applied to control a three-stage eighteen-level hybrid inverter, which has been designed with a maximum number of symmetrical levels. The inverter has a two-level main stage built using a conventional six-switch inverter and medium- and low- voltage three-level stages constructed using cascaded H-bridge cells. The distinctive feature of the proposed algorithm is its ability to avoid the undesirable high switching frequency for high- and medium- voltage stages despite the fact that the inverter's dc sources voltages are selected to maximize the number of levels by state redundancy elimination. The high- and medium- voltage stages switching algorithms have been developed to assure fundamental switching frequency operation of the high voltage stage and not more than few times this frequency for the medium voltage stage. The low voltage stage is controlled using a SVPWM to achieve the reference voltage vector exactly and to set the order of the dominant harmonics. The inverter has been constructed and the control algorithm has been implemented. Test results show that the proposed algorithm achieves the desired features and all of the major hypotheses have been verified.

• 전력전자학회논문지
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• 제14권4호
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• pp.307-314
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• 2009

본 논문에서는 풀-브리지 인버터의 앞단에 DC 전압원과 스위치를 추가하여 다단의 출력전압을 형성시킬 수 있는 멀티레벨 인버터를 제안한다. 제안된 회로에서 풀-브리지 인버터는 출력전압의 극성을 결정하게 되고 추가된 스위치의 동작에 의해 출력전안의 레벨 수를 정의할 수 있다. 제안된 방식은 동일 레벨의 출력전압을 형성시키는 경우 기존 멀티레벨 인버터에 비해 스위치 소자수를 저감 시킬 수 있는 장점을 가진다. 제안된 인버터의 타당성 검증을 위해 시뮬레이션 및 시작품을 이용한 실험 결과를 제시한다.

• Journal of Power Electronics
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• 제14권4호
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• pp.671-677
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• 2014

In this paper, a new basic unit is proposed. Then, a cascaded multilevel inverter basded on the series connection of n number of these new basic units is proposed. In order to generate all of the voltage levels (even and odd) at the output, three different algorithms to determine the magnitude of the dc voltage source are proposed. Reductions in the number of power switches, driver circuits and dc voltage sources in addition to increases in the numbr of output voltage levels are some of the advantages of the proposed cascaded multilevel inverter. These results are obtained through a comparison of the proposed inverter and its algorithms with an H-bridge cascaded multilevel inverter from the point of view of the number of power electronic devices. Finally, the capability of the proposed topology with its proposed algorithms in generating all of the voltage levels is verified through experimental results on a laboratorary prototype of a 49-level inverter.

• 한국환경보건학회지
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• 제34권1호
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• pp.27-33
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• 2008

In order to evaluate the magnetic field (MF) exposure level in residential areas near high voltage power lines, this research measured MF levels at 120 sites near high voltage transmission lines in the Busan region, Gwangju region, Daegu region and Changwon region from July to December, 2005, and compared and analyzed the efficiencies by measuring and applying the MF emission levels of underground cables and high voltage transmission lines. As a result of the investigation of the MF exposure level by the building usage, the average MF level of 17 locations at schools was $2.44{\pm}2.45mG;$ that of 10 locations at hospitals $6.21{\pm}12.39mG;$that of 76 locations at apartments $2.55{\pm}2.98mG;$ and that at kindergartens and infant houses $3.32{\pm}4.21mG$. MF exposure was analysed as a function of distance from the source and the MF levels directly below a source were $5.15{\pm}8.72mG$, those within 30 m were $3.10{\pm}3.32mG$, while those within 50 m were $2.45{\pm}2.38mG$, and within 100 m were $0.71{\pm}0.93mG$. In order to determine the difference of MF levels by the actual distance from high voltage transmission line within the same building, the evaluation of the floor position and the MF level has shown that the MF levels were highest in the order of roof, 4th floor, 3rd floor, 2nd floor and 1st floor. Comparison of MF emission intensity of underground cables and high voltage transmission lines, has shown that underground cables have an 86-94% of reduction ratio in MF compared to high voltage transmission lines, thus demonstrating higher efficiency.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.1042-1047
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• 2004

Voltage control is an essential part of the electric energy transmission and distribution system to maintain proper voltage limit at the consumer's terminal. Besides the generating units that provide the basic voltage control, there are many additional voltage-controlling agents e.g., shunt capacitors, shunt reactors, static VAr compensators, regulating transformers mentioned in [1], [2]. The most popular one, among all those agents for controlling voltage levels at the distribution and transmission system, is the on-load tap changer transformer. It serves two functions-energy transformation in different voltage levels and the voltage control. Artificial Neural Network (ANN) has been realized as a convenient tool that can be used in controlling the on load tap changer in the distribution transformers. Usage of the ANN in this area needs suitable training and testing data for performance analysis before the practical application. This paper briefly describes a procedure of processing the data to train an Artificial Neural Network (ANN) to control the tap changer operating decision of parallel transformers for a closed primary bus. The data set are used to train a two layer ANN using three different neural net learning algorithms, namely, Standard Backpropagation [3], Bayesian Regularization [4] and Scaled Conjugate Gradient [5]. The experimental results are presented including performance analysis.

• 대한전자공학회논문지SD
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• 제43권6호
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• pp.9-17
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• 2006

SoC(System-On-Chip) 시스템에서 초 저전력 시스템을 구현하기 위한 dynamic voltage and frequency scaling (DVFS)알고리즘에 사용될 시스템 버스의 다중 코어 전압 레벨을 생성해주는 새로운 다계층(multi-level) 코어 전압용 high-speed level up/down Shifter 회로를 제안한다. 이 회로는 내부 회로군과 외부 회로군 사이에서 서로 다른 전압레벨을 조정 접속하는 I/O용 level up/down shifter interface 회로로도 동시에 사용된다. 제안하는 회로는 인터페이스 접속에서 불가피하게 발생하는 속도감쇄와 Duty Ratio 불안정 문제를 최소화하는 장점을 갖고 있다. 본 회로는 500MHz의 입력 주파수에서 $0.6V\sim1.6V$의 다중 코어 전압을 각 IP들에서 사용되는 전압레벨로, 또는 그 반대의 동작으로 서로 Up/Down 하도록 설계하였다 그리고 제안하는 I/O 용 회로의 level up shifter는 500MHz의 입력 주파수에서 내부 코어 용 level up shifter의 출력전압인 1.6V를 I/O 전압인 1.8V, 2.5V, 3.3V로 전압레벨을 상승 하도록 설계하였으며, level down shifter는 반대의 동작으로 1Ghz의 입력 주파수에서 동작하도록 설계하였다. 시뮬레이션 및 결과는 $0.35{\mu}m$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process 와 65nm CMOS model 변수를 이용한 Hspice를 통하여 검증하였다. 또한, 제안하는 회로의 지연시간 및 파워소모 분석과 동작 주파수에 비례한 출력 전압의 Duty ratio 왜곡에 대한 연구도 하였다.

• 전력전자학회논문지
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• 제15권5호
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• pp.376-380
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• 2010

본 논문에서는 양방향 스위치를 가지는 기존의 5-레벨 인버터를 직렬 결합하여 다수의 출력 전압 레벨을 형성할 수 있는 멀티레벨 인버터 구조를 제안한다. 무엇보다도 제안된 회로의 입력 전압원 크기를 5의 배수로 구성함으로서 보다 많은 수의 레벨을 생성시킬 수 있다. 동일한 수의 출력 전압 레벨 형성시 기존의 Cascaded H-bridge cell 방식보다 스위칭 소자를 줄일 수 있어 시스템 크기, 비용, 전력 손실을 저감시킬 수 있는 장점을 가진다. 두 대의 5-레벨 인버터를 직렬 결합함으로써 25-레벨의 출력전압을 생성시킬 수 있는 인버터에 대한 특성을 분석하고 시뮬레이션과 실험을 통해 타당성을 검증한다.

• 품질경영학회지
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• 제23권4호
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• pp.128-147
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• 1995

An accelerated life testing(ALT) for aluminum electrolytic capacitors is conducted and analyzed. A testing equipment, which consists of part fixtures, relay board, controller, video bridge and microcomputer, is made for the ALT. Load factors are temperature with four levels and voltage with three levels. Base on 'optimized 4:2:1 plan', 2,000 electrolytic capacitors are allocated at 12 experimental conditions(; 4 levels of temperature ${\times}3$ levels of voltage), and the ALT is conducted. From the experimental results, an acceleration model is derived and acceleration factors are estimated. A discussion on the experimental results is included.