DOI QR코드

DOI QR Code

Wide Voltage Input Receiver with Hysteresis Characteristic to Reduce Input Signal Noise Effect

  • Biswas, Arnab Kumar (Department of Electronic Systems Engineering, Indian Institute of Science)
  • Received : 2012.09.21
  • Accepted : 2013.02.22
  • Published : 2013.10.31

Abstract

In this paper, an input receiver with a hysteresis characteristic that can work at voltage levels between 0.9 V and 5 V is proposed. The input receiver can be used as a wide voltage range Schmitt trigger also. At the same time, reliable circuit operation is ensured. According to the research findings, this is the first time a wide voltage range Schmitt trigger is being reported. The proposed circuit is compared with previously reported input receivers, and it is shown that the circuit has better noise immunity. The proposed input receiver ends the need for a separate Schmitt trigger and input buffer. The frequency of operation is also higher than that of the previously reported receiver. The circuit is simulated using HSPICE at 0.35-${\mu}m$ standard thin oxide technology. Monte Carlo analysis is conducted at different process conditions, showing that the proposed circuit works well for different process conditions at different voltage levels of operation. A noise impulse of ($V_{CC}/2$) magnitude is added to the input voltage to show that the receiver receives the correct logic level even in the presence of noise. Here, $V_{CC}$ is the fixed voltage supply of 3.3 V.

Keywords

References

  1. M. Steyaert and W. Sansen, "Novel CMOS Schmitt Trigger," Electron. Lett., vol. 22, no. 4, Feb. 1986, pp. 203-204. https://doi.org/10.1049/el:19860142
  2. S.-L. Chen and M.-D. Ker, "A New Schmitt Trigger Circuit in a $0.13-{\mu}m$ 1/2.5-V CMOS Process to Receive 3.3-V Input Signals," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 52, no. 7, July 2005, pp. 361-365. https://doi.org/10.1109/TCSII.2005.850409
  3. I.M Filanovsky and H. Baltes, "CMOS Schmitt Trigger Design," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 41, no. 1, Jan. 1994, pp. 46-49. https://doi.org/10.1109/81.260219
  4. M.J.S Smith, "On the Circuit Analysis of the Schmitt Trigger," IEEE J. Solid-State Circuits, vol. 23, no. 1, Feb. 1988, pp. 292-294. https://doi.org/10.1109/4.293
  5. T.-J. Lee, T.-Y. Chang, and C.-C. Wang, "Wide-Range 5.0/3.3/1.8-V I/O Buffer Using $0.35-{\mu}m$ 3.3-V CMOS Technology," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 4, Apr. 2009, pp. 763-772. https://doi.org/10.1109/TCSI.2008.2002921
  6. A.-J. Annema, G. Geelen, and P.C. de Jong, "5.5-V I/O in a 2.5-V $0.25-{\mu}m$ CMOS Technology," IEEE J. Solid-State Circuits, vol. 36, no. 3, Mar. 2001, pp. 528-538. https://doi.org/10.1109/4.910493
  7. G.P. Singh and R.B. Salem, "High-Voltage-Tolerant I/O Buffers with Low-Voltage CMOS Process," IEEE J. Solid-State Circuits, vol. 34, no. 11, Nov. 1999, pp. 1512-1525. https://doi.org/10.1109/4.799855
  8. D.-Y. Chen, "Design of a Mixed 3.3 V and 5 V PCI I/O Buffer," Proc. IEEE Int. ASIC Conf., 1996, pp. 336-339.
  9. C.-H. Chuang and M.-D. Ker, "Design on Mixed-Voltage-Tolerant I/O Interface with Novel Tracking Circuits in a $0.13-{\mu}m$ CMOS Technology," Proc. IEEE Int. Symp. Circuits Syst., vol. 2, May 2004, pp. 577-580.
  10. M.-D. Ker and S.-L. Chen, "Mixed-Voltage I/O Buffer with Dynamic Gate-Bias Circuit to Achieve $3{\times}V_{DD}$ Input Tolerance by Using $1{\times}V_{DD}$ Devices and Single $V_{DD}$ Supply," IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2005, pp. 524-525.
  11. M.-D. Ker and S.-L. Chen, "Design of Mixed-Voltage I/O Buffer by Using NMOS-Blocking Technique," IEEE J. Solid-State Circuits, vol. 41, no. 10, Oct. 2006, pp. 2324-2333. https://doi.org/10.1109/JSSC.2006.881546
  12. M. Takahashi et al., "3.3V-5V Compatible I/O Circuit without Thick Gate Oxide," Proc. IEEE Custom Integr. Circuits Conf., 1992, pp. 23.3.1-23.3.4.
  13. M. Pelgrom and E. Dijkmans, "A 3/5 V Compatible I/O Buffer," IEEE J. Solid-State Circuits, vol. 30, no. 7, July 1995, pp. 823-825. https://doi.org/10.1109/4.391124
  14. M.-D. Ker, S.-L. Chen, and C.-S. Tsai, "Overview and Design of Mixed-Voltage I/O Buffers with Low-Voltage Thin-Oxide CMOS Transistors," IEEE Trans. Circuits Syst. I, Regular Papers, vol. 53, no. 9, Sept. 2006, pp. 1934-1945. https://doi.org/10.1109/TCSI.2006.882816
  15. M.-D. Ker and C.-S. Tsai, "Design of 2.5 V/5 V Mixed-Voltage CMOS I/O Buffer with Only Thin Oxide Device and Dynamic N-Well Bias Circuits," Proc. IEEE Int. Symp. Circuits Syst., vol. 5, 2003, pp. 97-100.
  16. G. Liu, Y. Wang, and S. Jia, "A New Design of Mixed-Voltage I/O Buffers with Low-Voltage-Thin-Oxide CMOS Process," Proc. Int. Conf. ASIC, Oct. 2007, pp. 201-204.
  17. H. Sanchez et al., "A Versatile 3.3/2.5/1.8-V CMOS I/O Driver Built in a $0.2-{\mu}m$, 3.5-nm Tox, 1.8-V CMOS Technology," IEEE J. Solid-State Circuits, vol. 34, no. 11, Nov. 1999, pp. 1501-1511. https://doi.org/10.1109/4.799854
  18. M.-D. Ker and F.-L. Hu, "Design on Mixed-Voltage I/O Buffers with Consideration of Hot-Carrier Reliability," Proc. Int. Symp. VLSI-DAT, Apr. 2007, pp. 1-4.
  19. C.-C. Huang et al., "$(1/3){\times}VDD-to-(3/2){\times}VDD$ Wide-Range I/O Buffer Using $0.35-{\mu}m$ 3.3-V CMOS Technology," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 57, no. 2, Feb. 2010, pp. 126-130. https://doi.org/10.1109/TCSII.2010.2040311
  20. T.-J. Lee, W.-C. Chang, and C.-C. Wang, "Mixed-Voltage I/O Buffer Using $0.35-{\mu}m$ CMOS Technology," 15th IEEE Int. Conf. Electron., Circuits, Syst., Aug. 31-Sept. 3, 2008, pp. 850-853.

Cited by

  1. Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat vol.34, pp.10, 2015, https://doi.org/10.1007/s00034-015-9980-0
  2. A PVT-independent Schmitt trigger with fully adjustable hysteresis threshold voltages for low-power 1-bit digitization applications vol.13, pp.17, 2013, https://doi.org/10.1587/elex.13.20160650