• 전력전자학회:학술대회논문집
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• 전력전자학회 1996년도 창립기념 전력전자학술발표회 논문집
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• pp.71-75
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• 1996

As the Three-level ZVS PWM DC-DC converter operates likewise full-bridge ZVS PWM DC-DC converter and the blocking voltage of each switching device is a half of the DC-link voltage, it is suitable for the high imput voltage applications. However, it has some problems as follows; The blocking voltage of each devices is unbalanced and it causes the power losses of the inner switching devices to be increased. Also, it has narrow load range so that the switching losses and the efficiency are reduced as it goes to the light load. This paper presents an nove Three-level ZVS PWM DC-DC converter, which can reduce the overvoltage of the outer switches, eliminate the unbalance of the voltage sharing between the switches at turn-off due to the stray inductances, and operate from no load to full load. The characteristics and the performances of the proposed Three-level ZVS PWM DC-DC converter are verified by simulation and experimental results

• Journal of Power Electronics
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• 제8권3호
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• pp.248-258
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• 2008

The Voltage Source Converter (VSC) is replacing the conventional line commutated current source converters in High Voltage DC (HVDC) transmission systems. The control of a two-level voltage source converter and its design dealt with HVDC systems and various factors such as reactive power, power factor, and harmonics distortion are discussed in detail. Simulation results are given for the two-level converter and designed control is used for bidirectional power flow. The harmonics minimization is taken by extending the 6-pulse VSC to multipulse voltage source converters. The control is also tested and simulated for a 12-pulse voltage source converter to minimize the harmonic distortion in AC currents.

• 조명전기설비학회논문지
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• 제27권4호
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• pp.8-15
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• 2013

This paper proposes a DC-link voltage variation compensation method for a 3-level single phase converter for high-speed trains. Since 3-level NPC(Neutral Point Clamped) type converters have the split DC-link causing the inherent problem of voltage fluctuations in the upper and lower capacitors, reducing the voltage difference between the top and bottom capacitors is required. In this paper, compensation time proportional to the voltage difference is added to PWM switching time to solve the voltage variation. The compensation time is obtained by a PI controller. Simulation results demonstrate the validity of the proposed method.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.183-187
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• 2005

A Zero-Voltage-Switching(ZVS) Three-Level Converter realizes ZVS for the switches with the use of the leakage inductance(or external resonant inductance) and the output capacitors of the switches, however; the rectifier diodes suffer from recovery which results in oscillation and voltage spike. In order to solve this problem, this paper proposes a novel ZVS Three-Level converter, which introduces two clamping diodes to the basic Three-Level converter to eliminate the oscillation and clamp the rectified voltage to the reflected input voltage, the proposed ZVS Three-Level converter can be simplified by removing the two freewheeling diodes.

• 대한전기학회논문지
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• 제45권4호
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• pp.535-542
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• 1996

A zero voltage switching (ZVS) three level auxiliary resonant commutated pole inverter (ARCPI) is presented for high power GTO inverters. The concept of ARCP for two level inverter is extended to the three inverter. The proposed auxiliary commutation circuit consists of one resonant inductor and two bi-directional switches, which provides ZVS condition to the main devices without increasing device voltage or current stresses. The auxiliary device operates with zero current switching (ZCS) which enables use of the low cost thyristors. The proposed ARCPI can handle higher voltage and higher power (1-10MVA) comparing to the two level one. Operation and analysis of the ARCPI are illustrated and the features are compared o those of the snubber circuit incorporated three level inverter. Experimental results with 10kW, 4kHz prototype are presented to verify the principle of operation. (author). refs., figs., tab.

• 한국초전도ㆍ저온공학회논문지
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• 제14권3호
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• pp.43-47
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• 2012

A linear compressor generates pulsating pressure and oscillating flow in a cryocooler such as Stirling cryocooler and pulse tube refrigerator. It is driven by AC power source and designed to operate at resonance of piston motion. The driving voltage level is determined by electric parameters of resistance, inductance and thrust constant of linear motor. From voltage equation on linear motor, the power factor of driving power is inherently less than 1. The phase difference between voltage and current of supplied power can be zero using capacitor and this can minimize a supply voltage level. Especially, the linear compressor of kW class requires high voltage and thus can cause a difficulty in selecting power supply unit due to limitation of voltage level. The capacitor in driving electric circuit is useful to settle this problem. In this study, the electric circuit of linear compressor is analytically investigated with assumption of mechanical resonance. The electric parameters of commercial linear motor are used in the analysis. The effects of capacitor on driving voltage level and power factor are investigated. From analytic results, it is shown that the voltage level can be mimized with using capacitor in driving electric circuit.

• 대한전자공학회논문지SD
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• 제43권6호
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• pp.9-17
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• 2006

SoC(System-On-Chip) 시스템에서 초 저전력 시스템을 구현하기 위한 dynamic voltage and frequency scaling (DVFS)알고리즘에 사용될 시스템 버스의 다중 코어 전압 레벨을 생성해주는 새로운 다계층(multi-level) 코어 전압용 high-speed level up/down Shifter 회로를 제안한다. 이 회로는 내부 회로군과 외부 회로군 사이에서 서로 다른 전압레벨을 조정 접속하는 I/O용 level up/down shifter interface 회로로도 동시에 사용된다. 제안하는 회로는 인터페이스 접속에서 불가피하게 발생하는 속도감쇄와 Duty Ratio 불안정 문제를 최소화하는 장점을 갖고 있다. 본 회로는 500MHz의 입력 주파수에서 $0.6V\sim1.6V$의 다중 코어 전압을 각 IP들에서 사용되는 전압레벨로, 또는 그 반대의 동작으로 서로 Up/Down 하도록 설계하였다 그리고 제안하는 I/O 용 회로의 level up shifter는 500MHz의 입력 주파수에서 내부 코어 용 level up shifter의 출력전압인 1.6V를 I/O 전압인 1.8V, 2.5V, 3.3V로 전압레벨을 상승 하도록 설계하였으며, level down shifter는 반대의 동작으로 1Ghz의 입력 주파수에서 동작하도록 설계하였다. 시뮬레이션 및 결과는 $0.35{\mu}m$ CMOS Process, $0.13{\mu}m$ IBM CMOS Process 와 65nm CMOS model 변수를 이용한 Hspice를 통하여 검증하였다. 또한, 제안하는 회로의 지연시간 및 파워소모 분석과 동작 주파수에 비례한 출력 전압의 Duty ratio 왜곡에 대한 연구도 하였다.

• Journal of Power Electronics
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• 제18권5호
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• pp.1303-1314
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• 2018

To match the dynamic lower voltage of a fuel cell stack and the required constant higher voltage (400V) of a DC bus, an H-type structural Boost three-level DC-DC converter with a wide voltage-gain range (HS-BTL) is presented in this paper. When compared with the traditional flying-capacitor Boost three-level DC-DC converter, the proposed converter can obtain a higher voltage-gain and does not require a complicate control for the flying-capacitor voltage balance. Moreover, the proposed converter, which can draw a continuous and low-rippled current from an input source, has the advantages of a wide voltage-gain range and low voltage stress for power semiconductors. The operating principle, parameters design and a comparison with other converters are presented and analyzed. Experimental results are also given to verify the aforementioned characteristics and theoretical analysis. The proposed converter is suitable for application of fuel cell systems.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2001년도 전력전자학술대회 논문집
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• pp.475-478
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• 2001

In performing the three-level SVPWM, it is nearly impossible to control the neutral-point potential exactly to the half of the dc-link voltage at all times. Therefore the inverter would produce an erroneous output voltage by this voltage unbalance. So the voltage unbalance has to be compensated in doing PWM, when the voltage unbalance occurs whether it is small or large, to make the inverter output voltage follow the reference voltage exactly the same. In this paper, a new compensating method for the neutral-point potential variation in a three-level inverter space vector PWM (SVPWM) is presented. By using the proposed method, the output voltage of the inverter can be made same as the reference voltage and thus the current and torque ripple of the inverter driven motor can be greatly improved even if the voltage unbalance is quite large. The proposed method is verified experimentally with a 3-level IGBT inverter.

• 전기학회논문지
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• 제65권2호
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• pp.311-318
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• 2016

This paper is a study on the neutral point voltage balancing of the three-phase 3-level T-type inverter using the predictive control techniques. Recently, multi-level inverter has been attracting attention as the advantages such as efficiency improving and harmonic reduction. Especially, the T-type inverter topology is advantageous in low DC-link voltage. However, in case of the prediction control, it takes a lot of time, because there exist 27 voltage vectors and it has to be calculated according to the respective voltage vectors. Therefore, in this paper, we propose a method to implement predictive control techniques while reducing the operation time. In order to reduce the operation time, the predictive control is implemented by using the minimum voltage vector except for the unnecessary voltage vector. The result of the implemented predictive control is added to the SPWM by using the offset voltage. It was verified through simulation and experimental results.