• Journal of Power Electronics
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• 제16권5호
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• pp.1904-1917
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• 2016

The moving average filter (MAF) is widely utilized to improve the disturbance rejection capability of phase-locked loops (PLLs). This is of vital significance for the grid-integration and stable operation of power electronic converters to electric power systems. However, the open-loop bandwidth is drastically reduced after incorporating a MAF into the PLL structure, which makes the dynamic response sluggish. To overcome this shortcoming, some new techniques have recently been proposed to improve the transient response of MAF-based PLLs. In this paper, a comprehensive performance comparison of advanced MAF-based PLL algorithms is presented. This comparison includes HPLL, MPLC-PLL, QT1-PLL, and DMAF-PLL. Various disturbances, such as grid voltage sag, voltage flicker, harmonics distortion, phase-angle and frequency jumps, DC offsets and noise, are considered to experimentally test the dynamic performances of these PLL algorithms. Finally, an improved positive sequence extraction method for a HPLL under the frequency jumps scenario is presented to compensate for the steady-state error caused by non-frequency adaptive DSC, and a satisfactory performance has been achieved.

• 전력전자학회논문지
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• 제17권5호
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• pp.401-408
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• 2012

A simple on-line elimination strategy of the dead time and inverter nonlinearity using the current slope information is presented for a PWM inverter-fed IPMSM (Interior Permanent Magnet Synchronous Motor) drive. In a PWM inverter-fed IPMSM drive, a dead time is inserted to prevent a breakdown of switching device. This distorts the inverter output voltage, resulting in a current distortion and torque ripple. In addition to the dead time, inverter nonlinearity exists in switching devices of the PWM inverter, which is generally dependent on operating conditions such as the temperature, DC link voltage, and current. The proposed scheme is based on the fact that the d-axis current ripple is mainly caused by the dead time and inverter nonlinearity. To eliminate such an influence, the current slope information is determined. The obtained current slope information is processed by the PI controller to estimate the disturbance caused by the dead time and inverter nonlinearity. The overall system is implemented using DSP TMS320F28335 and the validity of the proposed algorithm is verified through the simulation and experiments. Without requiring any additional hardware, the proposed scheme can effectively eliminate the dead time and inverter nonlinearity even in the presence of the parameter uncertainty.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.520-523
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• 2004

A phase-locked loop control system designed by using the linear quadratic regulator approach is presented in this paper. The system thus designed is optimal system when system is in locked state and the parameter value of loop filter which is an active PI filter can be obtained easily. By considering the structure of loop filter of phase-locked loop is included in the process to be controlled, a type 1 servo system can be constructed when voltage control oscillator is considered as an integrator. The integral gain of the proposed system obtained by linear quadratic regulator approach can be used as an optimal value to design the parameter of loop filter. The implemented result in controlling the second-order lag pressure process by using the proposed scheme show that the system response is fast with no overshoot and no steady-state error. Furthermore, the experimental results are also shown in term of output disturbance effect rejection, tracking and process parameter changed.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.559-568
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• 2017

Harmonic/inter-harmonic detection and analysis is an important issue in power system signal processing. This paper proposes a fast algorithm based on matching pursuit (MP) sparse signal decomposition, which can be employed to extract the harmonic or inter-harmonic components of a distorted electric voltage/current signal. In the MP iterations, the method extracts harmonic/inter-harmonic components in order according to the spectrum peak. The Fast Fourier Transform (FFT) and nonlinear optimization techniques are used in the decomposition to realize fast and accurate estimation of the parameters. First, the frequency estimation value corresponding to the maxim spectrum peak in the present residual is obtained, and the phase corresponding to this frequency is searched in discrete sinusoids dictionary. Then the frequency and phase estimations are taken as initial values of the unknown parameters for Nelder-Mead to acquire the optimized parameters. Finally, the duration time of the disturbance is determined by comparing the inner products, and the amplitude is achieved according to the matching expression of the harmonic or inter-harmonic. Simulations and actual signal tests are performed to illustrate the effectiveness and feasibility of the proposed method.

• Journal of Electrical Engineering and Technology
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• 제12권1호
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• pp.385-395
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• 2017

A new digitized decoupled dual-axis micro dynamically tuned gyroscope with three equilibrium rings (TMDTG) is proposed which can eliminate the constant torque disturbance (CTD) caused by the double rotation frequency of a driving shaft with a micro dynamically tuned gyroscope with one equilibrium ring (MDTG). A mechanical and kinematic model of the TMDTG is theoretically analyzed and the structure parameters are optimized in ANSYS to demonstrate reliability. By adjusting the thickness of each equilibrium ring, the CTD can be eliminated. The digitized model of the TMDTG system is then simulated and examined using MATLAB. Finally, a digitized prototype based on FPGA is created. The gyroscope can be dynamically tuned by adjusting feedback voltage. Experimental results show the TMDTG has good performance with a scale factor of $283LSB/^{\circ}/s$ in X-axis and $220LSB/^{\circ}/s$ in Y-axis, respectively. The scale factor non-linearity is 0.09% in X-axis and 0.13% in Y-axis. Results from analytical models, simulations, and experiments demonstrate the feasibility of the proposed TMDTG.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.119-121
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• 2008

This paper is proposed a high Performance speed control of the synchronous reluctance motor through the SV-PWM(Space Vector Pulse Width Modulation) of FAM-PI(Fuzzy Adaptive Mechanism-PI). SV-PWM is controlled using FAM-PI control. SV-PWM can be maximum used maximum do link voltage and is excellent control method due to characteristic to reducing harmonic more than others. Fuzzy control has a advantage which can be robustly controlled. FAM-PI controller is changed fixed gain of PI controller using fuzzy adaptive mechanism(FAM) to match operating condition. The results on a speed controller of IPMSM are presented to show the effectiveness of the proposed gain tuner. And this controller is better than the fixed gains one in terms of robustness, even under great variations of operating conditions and load disturbance.

• 전력전자학회논문지
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• 제11권1호
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• pp.65-71
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• 2006

본 논문에서는 BLDC 전동기 센서리스 드라이브의 성능 향상을 위한 새로운 전동기 제어 기법을 제안한다. 최근 센서리스 제어방법의 주류를 이루고 있는 단자전압을 이용하는 방식들은 전동기를 동기 모드로 운전할 때 과도한 전압이 인가되면, 회전자 위치를 정확하게 검출할 수 없다. 특히 과도상태영역에서의 응답특성이 좋지 않다. 따라서 본 논문에서는 미지 입력인 역기전력을 추가적인 시스템의 상태로 모델링하고, 전체 시스템을 역기전력에 대한 미분방정식 형태 외란 모델을 도입한 확장 상태방정식으로 표현함으로서 얻어지는 상태관측기를 통하여 전동기의 속도 및 회전자 위치를 추정하는 새로운 알고리즘을 제안한다.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2001년도 학술대회논문집
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• pp.65-72
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• 2001

Power system stabilizer act efficiently to damp the electromechanical oscillations in interconnected power systems. This paper presents an algorithm for the optimal parameter selection of a power system stabilizer in two-area power systems with a series HVDC link. This method is one of the classical techniques by allocating properly pole-zero positions to fit as closely as desired the ideal phase lead between the voltage reference and the generator electrical power and by changing the gain to produce a necessary damping torque over the matched frequency range. Control of HVDC converter and inverter are used a constant current loop. Proper parameters of PI controllers are obtain based on the Root-locus technique in other to have sufficient speed and stability margin to cope with charging reference values and disturbance. The small signal stability arid transient stability studies using the PSS parameters obtained from this method show that a natural oscillation frequency of the studycase system is adequately damped. Also the simulation results using the HVDC converter and inverter parameters obtained from this proposed method show proper current control characteristics. The simulation used in the paper was performed by the Power System Toolbox software program based on MATLAB.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2009년도 제40회 하계학술대회
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• pp.997_998
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• 2009

Nowadays DC-DC converter has been used widely in electronic production. It has a high requirement in wide input voltage, load variations, stability, providing a fast transient response and the most important thing is that it can be applied easily and efficiently. However, it is not easy to be controlled because of nonlinear system. This study introduces a fuzzy linear control design method for nonlinear systems with optimal $H^{\infty}$ robustness performance. First, the Takagi and Sugeno fuzzy linear model is employed to approximate a nonlinear system. Next, based on the fuzzy linear model, a fuzzy controller is developed to stabilize the nonlinear system, and at the same time the effect of external disturbance on control performance is attenuated to a minimum level. Thus based on the fuzzy linear model, ��$H^{\infty}$ performance design can be achieved in nonlinear control systems. Linear matrix inequality (LMI) techniques are employed to solve this robust fuzzy control problem. PI control structure is used and the control gains are determined based on $H^{\infty}$ control.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.781-792
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• 2016

This paper presents a new approach to enhance the data retention of logic-compatible embedded DRAMs. The memory bit-cell in this work consists of two logic transistors implemented in generic triple-well CMOS process. The key idea is to use the parasitic junction capacitance built between the common cell-body and the data storage node. For each write access, a voltage transition on the cell-body couples up the data storage levels. This technique enhances the data retention and the read performance without using additional cell devices. The technique also provides much strong immunity from the write disturbance in the nature. Measurement results from a 64-kbit eDRAM test chip implemented in a 130 nm logic CMOS technology demonstrate the effectiveness of the proposed circuit technique. The refresh period for 99.9% bit yield measures $600{\mu}s$ at 1.1 V and $85^{\circ}C$, enhancing by % over the conventional design approach.