• Title/Summary/Keyword: Viterbi Decoder

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Full Data-rate Viterbi Decoder for DAB Receiver (최대 데이터율을 지원하는 DAB 수신기용 Viterbi 디코더의 설계)

  • 김효원;구오석;류주현;윤대희
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.6C
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    • pp.601-609
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    • 2002
  • The efficient Viterbi decoder that supports full data-rate output of DAB system was proposed. Viterbi decoder consumes lots of computational load and should be designed to be fast specific hardware. In this paper, SST scheme was adopted for Viterbi decoder with puncturing to reduced the power consumption. Puncturing vector tables are modified and re-arranged to be designed by a hardwired logic to save the system area. New re-scaling scheme which uses the fact that the difference of the maximum and minimum of the path metric values is bounded is proposed. The proposed re-scaling scheme optimizes the wordlength of path metric memory and greatly reduces the computational load for re-scaling by controlling MSB of path metric memory. Another saving of computation is done by proposed algorithm for branch metric calculation, which makes use of pre-calculated metric values. The designed Viterbi decoder was synthesized using SAMSUNG 0.35$\mu$ standard cell library and occupied small area and showed lower power consumption.

Implementation of a Viterbi Decoder Operated in the 1000Base-T (1000Base-T에서 동작하는 Viterbi Decoder 구현)

  • Jung, Jae-woo;Chung, Hae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2013.10a
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    • pp.41-44
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    • 2013
  • As appearance of high-quality service such as UDTV application, high-speed and high-capacity communication services are required. For this, communication systems increase the data processing speed and use various error correction techniques. In this paper, we implement the Viterbi decoder applied in 1000BASE-T with 4 pairs UTP cable. The minimum operating speed of the Viterbi decoer should be more than 125 MHz because 125 MHz PAM-5 signal is transmitted on each pair of cables in 1000BASE-T. To do this, we implement the decoder by using the pipeline and parallel processing and verify the operation with 125 MHz by using a logic analyzer. Finally, we will show that the decoder recovers the original data for the added random error data.

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A Viterbi Decoder with Efficient Memory Management

  • Lee, Chan-Ho
    • ETRI Journal
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    • v.26 no.1
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    • pp.21-26
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    • 2004
  • This paper proposes a new architecture for a Viterbi decoder with an efficient memory management scheme. The trace-back operation is eliminated in the architecture and the memory storing intermediate decision information can be removed. The elimination of the trace-back operation also reduces the number of operation cycles needed to determine decision bits. The memory size of the proposed scheme is reduced to 1/($5{\times}$ constraint length) of that of the register exchange scheme, and the throughput is increased up to twice that of the trace-back scheme. A Viterbi decoder complying with the IS-95 reverse link specification is designed to verify the proposed architecture. The decoder has a code rate of 1/3, a constraint length of 9, and a trace-forward depth of 45.

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A SPEC-T Viterbi decoder implementation with reduced-comparison operation (비교 연산을 개선한 SPEC-T 비터비 복호기의 구현)

  • Bang, Seung-Hwa;Rim, Chong-Suck
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.7 s.361
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    • pp.81-89
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    • 2007
  • The Viterbi decoder, which employs the maximum likelihood decoding method, is a critical component in forward error correction for digital communication system. However, lowering power consumption on the Viterbi decoder is a difficult task since the number of paths calculated equals the number of distinctive states of the decoder and the Viterbi decoder utilizes trace-back method. In this paper, we propose a method which minimizes the number of operations performed on the comparator, deployed in the SPEC-T Viterbi decoder implementation. The proposed comparator was applied to the ACSU(Add-Compare-Select Unit) and MPMSU(Minimum Path Metric Search Unit) modules on the decoder. The proposed ACS scheme and MPMS scheme shows reduced power consumption by 10.7% and 11.5% each, compared to the conventional schemes. When compared to the SPEC-T schemes, the proposed ACS and MPMS schemes show 6% and 1.5% less power consumption. In both of the above experiments, the threshold value of 26 was applied.

VLSI Design of SOVA Decoder for Turbo Decoder (터보복호기를 위한 SOVA 복호기의 설계)

  • Kim, Ki-Bo;Kim, Jong-Tae
    • Proceedings of the KIEE Conference
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    • 2000.07d
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    • pp.3157-3159
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    • 2000
  • Soft Output Viterbi Algorithm is modification of Viterbi algorithm to deliver not only the decoded codewords but also a posteriori probability for each bit. This paper presents SOVA decoder which can be used for component decoder of turbo decoder. We used two-step SMU architectures combined with systolic array traceback methods to reduce the complexity of the design. We followed the specification of CDMA2000 system for SOVA decoder design.

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Design of R=1/2, K=7 Type High Speed Viterbi Decoder with Circularly Connected 2-D Analog Parallel Processing Cell Array (아날로그 2차원 셀의 순환형 배열을 이용한 R=l/2. K=7형 고속 비터비 디코더 설계)

  • 손홍락;김형석
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.11
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    • pp.650-656
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    • 2003
  • A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing ceil array Is proposed. The proposed Viterbi .decoder has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram, the output column of the analog processing cells is connected to the decoding column, and thus, the output(last) column becomes a column right before the decoding(first) column. The reference input signal given at a decoding column is propagated to the whole network while Its magnitude is reduced by the amount of a error metric on each branch. The circuit-based decoding is done by adding a trigger signals of same magnitudes to disconnect the path corresponding to logic 0 (or 1) and by observing its effect at an output column (the former column of the decoding column). The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

Low Power Embedded Memory Design for Viterbi Decoder with Energy Optimized Write Operation (쓰기 동작의 에너지 감소를 통한 비터비 디코더 전용 저전력 임베디드 SRAM 설계)

  • Tang, Hoyoung;Shin, Dongyeob;Song, Donghoo;Park, Jongsun
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.11
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    • pp.117-123
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    • 2013
  • By exploiting the regular read and write access patterns of embedded SRAM memories inside Viterbi decoder, the memory architecture can be efficiently modified to reduce the power consumption of write operation. According to the experimental results with 65nm CMOS process, the proposed embedded memory used for Viterbi decoder achieves 30.84% of power savings with 8.92% of area overhead compared to the conventional embedded SRAM approaches.

Performance of the Viterbi Decoder using Analog Parallel Processing circuit with Reference position (아날로그 병렬 처리 망을 이용한 비터비 디코더의 기준 입력 인가위치에 따른 성능 평가)

  • Kim, Hyung-Jung;Kim, In-Cheol;Lee, Wnag-Hee;Kim, Hyong-Suk
    • Proceedings of the KIEE Conference
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    • 2006.10c
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    • pp.378-380
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    • 2006
  • A high speed Analog parallel processing-based Viterbi decoder with a circularly connected 2D analog processing cell array is proposed. It has a 2D parallel processing structure in which an analog processing cell is placed at each node of trellis diagram is connected circulary so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error corrections, has a shorter latency and requires no path memories. In this parer, the performance of error correction as a reference position with the Analog parallel processing-based Viterbi decoder is testd via the software simulation

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Design of Viterbi Decoder using Circularly-connected Analog Parallel Processing Networks (순환형 아날로그 병렬처리 회로망에 의한 비터비 디코더회로 설계)

  • 손홍락;박선규;김형석
    • Proceedings of the IEEK Conference
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    • 2003.07b
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    • pp.1173-1176
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    • 2003
  • A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing cell array is proposed. It has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram. The constraints' length of trellis diagram is connected circularly so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

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Parallel Decoder Module for Digital-Information Translation of Optical Disc (광디스크 디지털 정보 전송을 위한 병렬구조 디코더 모듈)

  • Kim, Jong-Man;Kim, Yeong-Min;Shin, Dong-Yong;Seo, Bum-Su
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.289-289
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    • 2010
  • Translation Characteristics of Digital Decoder utilizing the analog parallel processing circuit technology is designed. The fast parallel viterbi decoder system acted by a replacement of the conventional digital viterbi Decoder has good propagation. we are applied proposed analog viterbi decoder to decode PR signal for DVD and analyze the specific circuit and signal characteristics.

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