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A SPEC-T Viterbi decoder implementation with reduced-comparison operation  

Bang, Seung-Hwa (R&D Team, INTEGMA Co., Ltd)
Rim, Chong-Suck (Department of Computer Science and Engineering Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.7, 2007 , pp. 81-89 More about this Journal
Abstract
The Viterbi decoder, which employs the maximum likelihood decoding method, is a critical component in forward error correction for digital communication system. However, lowering power consumption on the Viterbi decoder is a difficult task since the number of paths calculated equals the number of distinctive states of the decoder and the Viterbi decoder utilizes trace-back method. In this paper, we propose a method which minimizes the number of operations performed on the comparator, deployed in the SPEC-T Viterbi decoder implementation. The proposed comparator was applied to the ACSU(Add-Compare-Select Unit) and MPMSU(Minimum Path Metric Search Unit) modules on the decoder. The proposed ACS scheme and MPMS scheme shows reduced power consumption by 10.7% and 11.5% each, compared to the conventional schemes. When compared to the SPEC-T schemes, the proposed ACS and MPMS schemes show 6% and 1.5% less power consumption. In both of the above experiments, the threshold value of 26 was applied.
Keywords
VLSI design; Viterbi decoder; low-power; SPEC-T algorithm;
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