Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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A SPEC-T Viterbi decoder implementation with reduced-comparison operation

비교 연산을 개선한 SPEC-T 비터비 복호기의 구현

  • 방승화 ((주)인테그마 연구개발팀) ;
  • 임종석 (서강대학교 컴퓨터공학과)
  • Published : 2007.07.25
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Abstract

The Viterbi decoder, which employs the maximum likelihood decoding method, is a critical component in forward error correction for digital communication system. However, lowering power consumption on the Viterbi decoder is a difficult task since the number of paths calculated equals the number of distinctive states of the decoder and the Viterbi decoder utilizes trace-back method. In this paper, we propose a method which minimizes the number of operations performed on the comparator, deployed in the SPEC-T Viterbi decoder implementation. The proposed comparator was applied to the ACSU(Add-Compare-Select Unit) and MPMSU(Minimum Path Metric Search Unit) modules on the decoder. The proposed ACS scheme and MPMS scheme shows reduced power consumption by 10.7% and 11.5% each, compared to the conventional schemes. When compared to the SPEC-T schemes, the proposed ACS and MPMS schemes show 6% and 1.5% less power consumption. In both of the above experiments, the threshold value of 26 was applied.

비터비 복호기는 디지털 통신 시스템에서 순방향 오류 정정을 위해서 사용하는 핵심적인 부분으로 최우 추정 복호 방식의 알고리즘을 사용한다. 비터비 복호기는 복호기 상태의 개수만큼의 경로를 계산하고 역 추적하는 특성 때문에 저 전력화가 상당히 어렵다. 본 논문에서는 기존의 SPEC-T 알고리즘을 구현하는데 있어서 비교기의 동작을 최소화할 수 있는 효율적인 방법을 제안하고 ACS(Add-Compare-Select) 구조와 MPMS(Minimum Path Metric Search) 구조에 이를 적용하였다. 실험 결과, 제안한 ACS 구조와 MPMS 구조는 기존의 구조보다 전력 소모량이 임계 값 26에서 각각 최대 약 10.7%와 11.5% 감소하였고 SPEC-T 구조보다는 전력 소모량이 임계 값 26에서 각각 약 6%와 1.5% 더 감소하였다.

Keywords

References

  1. I. Kang and A. N. Willson Jr., 'Low-power Viterbi decoder for CDMA mobile terminals,' IEEE J. Solid-State Circuits, Vol. 33, pp. 473-482, Mar. 1998 https://doi.org/10.1109/4.661213
  2. Chi-Ying Tsui et. al., 'Low Power ACS Unit Design for the Viterbi Decoder,' ISCAS-99, pp. 137-140
  3. Ghoneima M., Sharaf K., Ragai H.F., El-Halim Zekry, 'Low power units for the Viterbi decoder,' the 43rd IEEE Midwest Symposium on Circuits and Systems, Vol. pp.412-415, August, 2000
  4. Kevin Page, Paul M. Chau, 'Improved Architectures for the Add-Compare-Select Operation in Long Constraint Length Viterbi Decoding,' IEEE J. Solid-State Circuits, Vol. 33, No. 1, Jan 1998
  5. M. A. Bree, D. E. Dodds, 'A Bit-Serial Architecture for a VLSI Viterbi Processor,' Conference Proc, WESCANEX 88, Digital Commun, pp.72-77, May 12, 1988
  6. J. B. Anderson and S. Mohan, 'Sequential coding algorithms: A survey and cost analysis,' IEEE Trans. Commun., Vol. 32, pp. 169-176, Feb. 1984 https://doi.org/10.1109/TCOM.1984.1096023
  7. S. J. Simmons, 'Breadth-first trellis decoding with adaptive effort,' IEEE Trans. Commun., Vol. 38, pp. 3-12, Jan. 1990 https://doi.org/10.1109/26.46522
  8. R. Henning and C. Chakrabarti, 'An approach for adaptively approximating the Viterbi algorithm to reduce power consumption while decoding convolutional codes,' IEEE Trans. Signal Processing, Vol. 52, no. 5, pp. 1443-1451, May 2004 https://doi.org/10.1109/TSP.2004.826163
  9. Fei Sun and Tong Zhang, 'Parallel High-Throughput Limited Search Trellis Decoder VLSI Desigin,' IEEE Trans. Very Large Scale Integr.(VLSI) Syst., Vol. 13, no. 9, Sept 2005
  10. Andrew J. Viterbi, 'Error bounds for convolutional codes and an asymptotically optimum decoding algorithm,' IEEE Trans. Inform. Theory, Vol. IT-13, pp. 260-269, April 1967
  11. Stephen B. Wicker, Error control systems for digital communication and storage, Prentice Hall, Inc,. 1995