• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.12
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• pp.1792-1798
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• 2017

Event Data Recorder(Car Black-Box) with WiFi dongle have been released, and the platform of the majority is the Linux platform. This is because the platform development is possible in little investment cost by reducing the source licensing costs by taking advantage of the open source. But utilizing Linux platform has the limitations of boot-up time and consuming processing power due to the limitation of battery capacity, to be cost-competitive to minimize the use of memory. In this paper, the real-time operating system(RTOS) is utilized to optimize these portions. MP4 encoder and Muxer are developed to be about ten seconds boot up and minimized memory. It has the advantages of operating at lower power consumption than the Linux utilizing WiFi dongle. Utilizing a WiFi dongle is to provide a progressive download feature on smart phones to lower product prices. But RTOS has the weakness in WiFi. Porting TCP /IP, Web and DHCP server and combination with the USB OTG Host interface by implementing the protocol stack are developed for WiFi. And also SPI NOR flash memory is utilized for faster boot time and cost reductions, low processing power to be consume. As the results, the developed proved the 10 seconds booting time, 24 frame rate/sec. and 10% lower power consumption.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.39 no.4
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• pp.347-357
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• 2003

This paper describes on the suppression of sea clutter on marine radar display using a cell-averaging CFAR(constant false alarm rate) technique, and on the analysis of radar echo signal data in relation to the estimation of ARPA functions and the detection of the shadow effect in clutter returns. The echo signal was measured using a X -band radar, that is located on the Pukyong National University, with a horizontal beamwidth of $$3.9^{\circ}$$, a vertical beamwidth of $20^{\circ}$, pulsewidth of $0.8 {\mu}s$ and a transmitted peak power of 4 ㎾ The suppression performance of sea clutter was investigated for the probability of false alarm between $l0-^0.25;and; 10^-1.0$. Also the performance of cell averaging CFAR was compared with that of ideal fixed threshold. The motion vectors and trajectory of ships was extracted and the shadow effect in clutter returns was analyzed. The results obtained are summarized as follows；1. The ARPA plotting results and motion vectors for acquired targets extracted by analyzing the echo signal data were displayed on the PC based radar system and the continuous trajectory of ships was tracked in real time. 2. To suppress the sea clutter under noisy environment, a cell averaging CFAR processor having total CFAR window of 47 samples(20+20 reference cells, 3+3 guard cells and the cell under test) was designed. On a particular data set acquired at Suyong Man, Busan, Korea, when the probability of false alarm applied to the designed cell averaging CFAR processor was 10$^{-0}$.75/ the suppression performance of radar clutter was significantly improved. The results obtained suggest that the designed cell averaging CFAR processor was very effective in uniform clutter environments. 3. It is concluded that the cell averaging CF AR may be able to give a considerable improvement in suppression performance of uniform sea clutter compared to the ideal fixed threshold. 4. The effective height of target, that was estimated by analyzing the shadow effect in clutter returns for a number of range bins behind the target as seen from the radar antenna, was approximately 1.2 m and the information for this height can be used to extract the shape parameter of tracked target..

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.68-74
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• 2009

In this paper, we propose an effective memory reduction algorithm to reduce the amount of reference frame buffer and memory bandwidth in video encoder and decoder. In general video codecs, decoded previous frames should be stored and referred to reduce temporal redundancy. Recently, reference frames are recompressed for memory efficiency and bandwidth reduction between a main processor and external memory. However, these algorithms could hurt coding efficiency. Several algorithms have been proposed to reduce the amount of reference memory with minimum quality degradation. They still suffer from quality degradation with fixed-bit allocation. In this paper, we propose an adaptive block-based min-max quantization that considers local characteristics of image. In the proposed algorithm, basic process unit is $8{\times}8$ for memory alignment and apply an adaptive quantization to each $4{\times}4$ block for minimizing quality degradation. We found that the proposed algorithm can obtain around 1.7% BD-bitrate gain and 0.03dB BD-PSNR gain, compared with the conventional fixed-bit min-max algorithm with 37.5% memory saving.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.9
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• pp.592-607
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• 2006

This paper proposes a technique to select processors and hardware IPs and to map the tasks into the selected processing elements, aming to achieve high performance with minimal system cost when multitask applications with real-time constraints are run on a multicore SoC. Such technique is called to 'Hardware-Software Cosynthesis Technique'. A cosynthesis technique was already presented in our early work [1] where we divide the complex cosynthesis problem into three subproblems and conquer each subproblem separately: selection of appropriate processing components, mapping and scheduling of function blocks to the selected processing component, and schedulability analysis. Despite good features, our previous technique has a serious limitation that a task monopolizes the entire system resource to get the minimum schedule length. But in general we may obtain higher performance in multitask multicore system if independent multiple tasks are running concurrently on different processor cores. In this paper, we present two mapping techniques, task mapping avoidance technique(TMA) and task mapping pinning technique(TMP), which are applicable for general cases with diverse operating policies in a multicore environment. We could obtain significant performance improvement for a multimedia real-time application, multi-channel Digital Video Recorder system and for randomly generated multitask graphs obtained from the related works.

• Journal of Internet Computing and Services
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• v.16 no.1
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• pp.1-8
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• 2015

Ultra-wide-angle wireless endoscopes are demonstrated in this paper. The endoscope is composed of an ultra-wide-angle camera module and wireless transmission module. A lens unit with the ultra-wide FOV of 162 degrees is designed and manufactured. The lens, image sensor, and camera processor unit are packaged together in a $3{\times}3{\times}9-cm3$ case. The wireless transmission modules are implemented based on UWB- and WiFi-based platform, respectively. The UWB-based module can transmit HD video to a computer in resolution of $2048{\times}1536$ (QXGA) and the frame rate of 15 fps in MJPEG compression mode. The maximum data transfer rate reaches 41.2 Mbps. The FOV and the resolution of the endoscope is comparable to a medical-grade endoscope. The FOV and resolution is ~3X and 16X higher than that of a commercial high-performance WiFi endoscope, respectively. The WiFi-based module streams out video to a smart device with th maximum date transfer rate of 1.5 Mbps at the resolution of $640{\times}480$ (VGA) and the frame rate of 30 fps in MJPEG compression mode. The implemented components show the feasibility of cheap medical-grade wireless electronic endoscopes, which can be effectively used in u-healthcare, emergency treatment, home-healthcare, remote diagnosis, etc.

• Journal of the Korea Society of Computer and Information
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• v.27 no.11
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• pp.181-190
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• 2022

In this paper, we use a LiDAR sensor and an image camera to detect a left-turning waiting vehicle in two ways, unlike the existing image-type or loop-type left-turn detection system, and a left-turn traffic signal corresponding to the waiting length of the left-turning lane. A system that can efficiently assign a system is introduced. For the LiDAR signal transmitted and received by the LiDAR sensor, the left-turn waiting vehicle is detected in real time, and the image by the video camera is analyzed in real time or at regular intervals, thereby reducing unnecessary computational processing and enabling real-time sensitive processing. As a result of performing a performance test for 5 hours every day for one week with an intersection simulation using an actual signal processor, a detection rate of 99.9%, which was improved by 3% to 5% compared to the existing method, was recorded. The advantage is that 99.9% of vehicles waiting to turn left are detected by the LiDAR sensor, and even if an intentional omission of detection occurs, an immediate response is possible through self-correction using the video, so the excessive waiting time of vehicles waiting to turn left is controlled by all lanes in the intersection. was able to guide the flow of traffic smoothly. In addition, when applied to an intersection in the outskirts of which left-turning vehicles are rare, service reliability and efficiency can be improved by reducing unnecessary signal costs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1778-1784
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• 2016

we improved the performance by parallelizing lane detection algorithms. Lane detection, as a intellectual assisting system, helps drivers make an alarm sound or revise the handle in response of lane departure. Four kinds of algorithms are implemented in order as following, Gaussian filtering algorithm so as to remove the interferences, gray conversion algorithm to simplify images, sobel edge detection algorithm to find out the regions of lanes, and hough transform algorithm to detect straight lines. Among parallelized methods, the data level parallelism algorithm is easy to design, yet still problem with the bottleneck. The high-speed data level parallelism is suggested to reduce this bottleneck, which resulted in noticeable performance improvement. In the result of applying actual road video of black-box on our parallel algorithm, the measurement, in the case of single-core, is approximately 30 Frames/sec. Furthermore, in the case of octa-core parallelism, the data level performance is approximately 100 Frames/sec and the highest performance comes close to 150 Frames/sec.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.1
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• pp.1-9
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into a H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel for the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks. The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit or a field synchronized with the A/D converter. The implemented H/W used the 54％(12943) LAB(Logic Array Block) and 9％(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation. that is. processing 60 fields/sec(30 frames/sec).

• Journal of the Korean Society for Nondestructive Testing
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• v.13 no.2
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• pp.20-30
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• 1993

Electric Speckle Pattern Interferometry (ESPI) using a CW-laser, a video system and an image processor was applied to the thermal coefficient measurements on free thermal expansions at high temperatures : ESPI provides the distribution of in-plane displacement resolved in a preselected direction. ESPI retains the merits of little or no surface preparation, no contact with the surface and the real-time presentation of interference fringes. Appling ESPI at high temperatures, several problem which caused the reduction of fringe visibility were encountered. The problem on the turbulence in the hot air surrounding high temperature objects will be solved by using a vacuum chamber. The background radiations from the objects were suppressed considerably by an interference filter. The problem on the oxidation of the object surface could't be solved. The interference fringe, whose spacings were calculated by FFT to avoid human error, were observable up to $800^{\circ}C$. The results measured by ESPI were nearly equal to the data which have already been published, up to about $800^{\circ}C$.

• The KIPS Transactions:PartA
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• v.14A no.5
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• pp.301-308
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• 2007

This paper proposes high performance coprocessor architecture for real time dense disparity computation based on a phase-based binocular stereo matching technique called local weighted phase-correlation(LWPC). The algorithm combines the robustness of wavelet based phase difference methods and the basic control strategy of phase correlation methods, which consists of 4 stages. For parallel and efficient hardware implementation, the proposed architecture employs SIMD(Single Instruction Multiple Data Stream) architecture for each functional stage and all stages work on pipelined mode. Such that the newly devised pipelined linear array processor is optimized for the case of row-column image processing eliminating the need for transposed memory while preserving generality and high throughput. The proposed architecture is implemented with Xilinx HDL tool and the required hardware resources are calculated in terms of look up tables, flip flops, slices, and the amount of memory. The result shows the possibility that the proposed architecture can be integrated into one chip while maintaining the processing speed at video rate.