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http://dx.doi.org/10.6109/jkiice.2016.20.9.1778

Design of Parallel Processing of Lane Detection System Based on Multi-core Processor  

Lee, Hyo-Chan (Department of Information and Communication Engineering, Hoseo University)
Moon, Dai-Tchul (Department of Information and Communication Engineering, Hoseo University)
Park, In-hag (System Centroid Inc.)
Heo, Kang (Department of Information and Communication Engineering, Hoseo University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.20, no.9, 2016 , pp. 1778-1784 More about this Journal
Abstract
we improved the performance by parallelizing lane detection algorithms. Lane detection, as a intellectual assisting system, helps drivers make an alarm sound or revise the handle in response of lane departure. Four kinds of algorithms are implemented in order as following, Gaussian filtering algorithm so as to remove the interferences, gray conversion algorithm to simplify images, sobel edge detection algorithm to find out the regions of lanes, and hough transform algorithm to detect straight lines. Among parallelized methods, the data level parallelism algorithm is easy to design, yet still problem with the bottleneck. The high-speed data level parallelism is suggested to reduce this bottleneck, which resulted in noticeable performance improvement. In the result of applying actual road video of black-box on our parallel algorithm, the measurement, in the case of single-core, is approximately 30 Frames/sec. Furthermore, in the case of octa-core parallelism, the data level performance is approximately 100 Frames/sec and the highest performance comes close to 150 Frames/sec.
Keywords
Multi-core; Parallel Processing; Lane Detection; Data Level Parallelism;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
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