• 마이크로전자및패키징학회지
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• 제19권4호
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• pp.39-43
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• 2012

Via-filling plating and through-hole plating are absolutely imperative for manufacturing of printed-wiring board. This Paper is introducing the latest developments of our company worked on the high-performance of acid copper plating additives for them.

• 한국표면공학회지
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• 제46권4호
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• pp.153-157
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• 2013

The defect like the void or seam is frequently generated in the PCB (Printed Circuit Board) Via-Filling plating inside via hole. The organic additives including the accelerating agent, inhibitor, leveler, and etc. are needed for the copper Via-Filling plating without this defect for the plating bath. However, the decomposition of the organic additive reduces the lifetime of the plating bath during the plating process, or it becomes the factor reducing the reliability of the Via-Filling. In this paper, the interaction of each organic additives and the decomposition of additive were discussed. As to the accelerating agent, the bis (3-sulfopropyl) disulfide (SPS) and leveler the Janus Green B (JGB) and inhibitor used the polyethlylene glycol 8000 (PEG). The research on the interaction of the organic additives and decomposition implemented in the galvanostat method. The additive decomposition time was confirmed in the plating process from 0 Ah/l (AmpereHour/ liter) to 100 Ah/l with the potential change.

• 한국표면공학회지
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• 제46권4호
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• pp.158-161
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• 2013

Recently, the weight reduction and miniaturization of the electronics have placed great emphasis. The miniaturization of PCB (Printed Circuit Board) as main component among the electronic components has also become progressed. The use of acid copper plating process for Via-Filling effectively forms interlayer connection in build-up PCBs with high-density interconnections. However, in the case of copper-via filled in a bath, which is greatly dependent on the effects of additives. This paper discusses effects of Cl ion on the filling of PCB vias with electrodeposited copper based on both electrochemical experiment and practical observation of cross sections of vias.

• 한국재료학회지
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• 제22권7호
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• pp.374-378
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• 2012

In an effort to overcome the problems which arise when fabricating high-aspect-ratio TSV(through silicon via), we performed experiments involving the void-free Cu filling of a TSV(10~20 ${\mu}m$ in diameter with an aspect ratio of 5~7) by controlling the plating DC current density and the additive SPS concentration. Initially, the copper deposit growth mode in and around the trench and the TSV was estimated by the change in the plating DC current density. According to the variation of the plating current density, the deposition rate during Cu electroplating differed at the top and the bottom of the trench. Specifically, at a current density 2.5 mA/$cm^2$, the deposition rate in the corner of the trench was lower than that at the top and on the bottom sides. From this result, we confirmed that a plating current density 2.5 mA/$cm^2$ is very useful for void-free Cu filling of a TSV. In order to reduce the plating time, we attempted TSV Cu filling by controlling the accelerator SPS concentration at a plating current density of 2.5 mA/$cm^2$. A TSV with a diameter 10 ${\mu}m$ and an aspect ratio of 7 was filled completely with Cu plating material in 90 min at a current density 2.5 mA/$cm^2$ with an addition of SPS at 50 mg/L. Finally, we found that TSV can be filled rapidly with plated Cu without voids by controlling the SPS concentration at the optimized plating current density.

• 한국재료학회지
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• 제22권7호
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• pp.335-341
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• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

• 한국재료학회지
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• 제23권10호
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• pp.550-554
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• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• 마이크로전자및패키징학회지
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• 제14권3호
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• pp.37-42
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• 2007

반도체 소자의 집적도가 높아짐에 따라 3D SiP에 대한 관심이 높아지고 전기도금법을 이용한 구리 via filling이 활발히 연구되어왔다. Via filling시 via 입구와 바닥에 전류밀도 차이로 인해 via 내부에 결함이 발생하기 쉽다. 여러 가지 유기물 첨가제와 전류인가 방식의 변화를 통한 via filling을 하였다. 첨가된 유기물은 PEG, SPS, JGB, PEI를 사용하였다. 유기물이 첨가된 용액을 이용하여 펄스와 역펄스 방법을 이용하여 via filling을 하였다. 유기물의 첨가에 따른 도금된 구리 입자의 크기 및 형상에 관하여 고찰하였으며 도금 후 via 시편의 단면을 FESEM으로 관찰하였다. JGB에 비하여 PEI를 사용한 경우 치밀한 도금층을 얻을 수 있었다. 2 step via filling을 사용한 경우 via filling 시간을 단축시킬 수 있었다.

• 마이크로전자및패키징학회지
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• 제22권4호
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• pp.99-104
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• 2015

비아 필링에 있어서 void나 seam 생성이 없이 비아를 채우는 것은 매우 중요한 사항으로 전류밀도, 전류모드, 첨가제 등을 변화시켜 결함없는 비아를 얻어왔다. 그러나 다양한 첨가제의 부산물이 오염의 원인이 되며 도금액의 수명을 줄이는 문제점이 있었다. 본 연구에서는 오염을 최소화하기 위하여 다른 첨가제가 없이 JGB만을 사용하여 JGB 농도와 전류밀도 변화에 따른 비아 필링 현상을 연구하였다. 지름이 $15{\mu}m$이며 종횡비 4인 비아가 사용되었으며 펄스전류를 이용하여 도금을 하였다. 전류밀도는 $10{\sim}20mA/cm^2$, JGB 농도는 0~25 ppm까지 변화시키면서 JGB 농도와 전류밀도와 의 상관관계를 mapping 하였다. 그로부터 지름이 $15{\mu}m$이며 종횡비 4인 비아 필링의 최적 조건을 확립하였다.

• 대한금속재료학회지
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• 제49권5호
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• 마이크로전자및패키징학회지
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• 제19권2호
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• pp.55-59
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• 2012

TSV 비아필링 과정이 진행되는 동안 내부에 void나 seam과 같은 결함이 빈번하게 발견되고 있다. 결함 없는 구리 비아필링을 위해서는 용액 내에 가속제, 억제제, 평활제 등의 유기물 첨가제가 필요하다. 공정과정중 유기물 첨가제의 분해로 인한 부산물로부터 기인한 오염은 디바이스의 신뢰도나 용액의 수명을 감소시키는 요인이 된다. 본 연구에서는 첨가제의 사용량을 줄이기 위하여 가속제와 억제제를 사용하지 않고 평활제만을 이용한 구리 비아필링에 관한 연구를 진행하였다. 세가지 종류의 첨가제(janus green B, methylene violet, diazine black)를 이용한 구리 전착에 관한 연구를 수행하였다. 각각의 첨가제에 따른 전기화학적 거동을 분석한 결과 도금속도적 측면에서 차이를 나타내는 것을 확인할 수 있었다. 비아필링 진행 후 단면을 분석하여 각각의 평활제가 비아필링에 미치는 영향을 확인하였으며, 그 특성은 다르게 나타나는 것을 확인할 수 있었다.