• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.39-43
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• 2012

Via-filling plating and through-hole plating are absolutely imperative for manufacturing of printed-wiring board. This Paper is introducing the latest developments of our company worked on the high-performance of acid copper plating additives for them.

• Journal of the Korean institute of surface engineering
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• v.46 no.4
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• pp.153-157
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• 2013

The defect like the void or seam is frequently generated in the PCB (Printed Circuit Board) Via-Filling plating inside via hole. The organic additives including the accelerating agent, inhibitor, leveler, and etc. are needed for the copper Via-Filling plating without this defect for the plating bath. However, the decomposition of the organic additive reduces the lifetime of the plating bath during the plating process, or it becomes the factor reducing the reliability of the Via-Filling. In this paper, the interaction of each organic additives and the decomposition of additive were discussed. As to the accelerating agent, the bis (3-sulfopropyl) disulfide (SPS) and leveler the Janus Green B (JGB) and inhibitor used the polyethlylene glycol 8000 (PEG). The research on the interaction of the organic additives and decomposition implemented in the galvanostat method. The additive decomposition time was confirmed in the plating process from 0 Ah/l (AmpereHour/ liter) to 100 Ah/l with the potential change.

• Journal of the Korean institute of surface engineering
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• v.46 no.4
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• pp.158-161
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• 2013

Recently, the weight reduction and miniaturization of the electronics have placed great emphasis. The miniaturization of PCB (Printed Circuit Board) as main component among the electronic components has also become progressed. The use of acid copper plating process for Via-Filling effectively forms interlayer connection in build-up PCBs with high-density interconnections. However, in the case of copper-via filled in a bath, which is greatly dependent on the effects of additives. This paper discusses effects of Cl ion on the filling of PCB vias with electrodeposited copper based on both electrochemical experiment and practical observation of cross sections of vias.

• Korean Journal of Materials Research
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• v.22 no.7
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• pp.374-378
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• 2012

In an effort to overcome the problems which arise when fabricating high-aspect-ratio TSV(through silicon via), we performed experiments involving the void-free Cu filling of a TSV(10~20 ${\mu}m$ in diameter with an aspect ratio of 5~7) by controlling the plating DC current density and the additive SPS concentration. Initially, the copper deposit growth mode in and around the trench and the TSV was estimated by the change in the plating DC current density. According to the variation of the plating current density, the deposition rate during Cu electroplating differed at the top and the bottom of the trench. Specifically, at a current density 2.5 mA/$cm^2$, the deposition rate in the corner of the trench was lower than that at the top and on the bottom sides. From this result, we confirmed that a plating current density 2.5 mA/$cm^2$ is very useful for void-free Cu filling of a TSV. In order to reduce the plating time, we attempted TSV Cu filling by controlling the accelerator SPS concentration at a plating current density of 2.5 mA/$cm^2$. A TSV with a diameter 10 ${\mu}m$ and an aspect ratio of 7 was filled completely with Cu plating material in 90 min at a current density 2.5 mA/$cm^2$ with an addition of SPS at 50 mg/L. Finally, we found that TSV can be filled rapidly with plated Cu without voids by controlling the SPS concentration at the optimized plating current density.

• Korean Journal of Materials Research
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• v.22 no.7
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• pp.335-341
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• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

• Korean Journal of Materials Research
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• v.23 no.10
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• pp.550-554
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• 2013

As continued scaling becomes increasingly difficult, 3D integration has emerged as a viable solution to achieve higher bandwidths and good power efficiency. 3D integration can be defined as a technology involving the stacking of multiple processed wafers containing integrated circuits on top of each other with vertical interconnects between the wafers. This type of 3D structure can improve performance levels, enable the integration of devices with incompatible process flows, and reduce form factors. Through silicon vias (TSVs), which directly connect stacked structures die-to-die, are an enabling technology for future 3D integrated systems. TSVs filled with copper using an electro-plating method are investigated in this study. DC and pulses are used as a current source for the electro-plating process as a means of via filling. A TiN barrier and Ru seed layers are deposited by plasma-enhanced atomic layer deposition (PEALD) with thicknesses of 10 and 30 nm, respectively. All samples electroplated by the DC current showed defects, even with additives. However, the samples electroplated by the pulse current showed defect-free super-filled via structures. The optimized condition for defect-free bottom-up super-filling was established by adjusting the additive concentrations in the basic plating solution of copper sulfate. The optimized concentrations of JGB and SPS were found to be 10 and 20 ppm, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.37-42
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• 2007

Copper deposition studies have been actively studied since interests on 3D SiP were increased. The defects inside via can be easily formed due to the current density differences on entrance, bottom and wall of via. So far many different additives and current types were discussed and optimized to obtain void-free copper via filling. In this research acid cupric sulfate plating bath containing additives such as PEG, SPS, JGB, PEI and wave current applied electroplating were examined. The size and shape of grain were influenced by the types of organic additives. The cross section of specimen were analyzed by FESEM. When PEI was added, the denser copper deposits were obtained. Electroplaing time was reduced when 2 step via filling was employed.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.4
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• pp.99-104
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• 2015

The requirement for success of via filling is its ability to fill via holes completely without producing voids or seams. Defect free via filling was obtained by optimizing plating conditions such as current mode, current density and additives. However, byproducts stemming from the breakdown of these organic additives reduce the lifetime of the devices and plating solutions. In this study, the relationship between JGB and current density on the copper via filling was investigated without the addition of other additives to minimize the contamination of copper via. AR 4 with $15{\mu}m$ diameter via were used for this study. The pulse current was used for the electroplating of copper and the current densities were varied from 10 to $20mA/cm^2$ and the concentrations of JGB were varied from 0 to 25 ppm. The map for the JGB concentration and current density was developed. And the optimum conditions for the AR 4 via filling with $15{\mu}m$ diameter were obtained.

• Korean Journal of Metals and Materials
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• v.49 no.5
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• pp.388-394
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• 2011

High speed copper filling into TSV (through-silicon-via) for three dimensional stacking of Si chips was investigated. For this study, a tapered via was prepared on a Si wafer by the DRIE (deep reactive ion etching) process. The via had a diameter of 37${\mu}m$ at the via opening, and 32${\mu}m$ at the via bottom, respectively and a depth of 70${\mu}m$. $SiO_2$, Ti, and Au layers were coated as functional layers on the via wall. In order to increase the filling ratio of Cu into the via, a PPR (periodic pulse reverse) wave current was applied to the Si chip during electroplating, and a PR (pulse reverse) wave current was applied for comparison. After Cu filling, the cross sections of the vias was observed by FE-SEM (field emission scanning electron microscopy). The experimental results show that the tapered via was filled to 100% at -5.85 mA/$cm^2$ for 60 min of plating by PPR wave current. The filling ratio into the tapered via by the PPR current was 2.5 times higher than that of a straight via by PR current. The tapered via by the PPR electroplating process was confirmed to be effective to fill the TSV in a short time.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.55-59
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• 2012

Defects such as voids or seams are frequently found in TSV via filling process. To achieve defect-free copper via filling, organic additives such as suppressor, accelerator and leveler were necessary in a copper plating bath. However, by-products stemming from the breakdown of these organic additives reduce the lifetime of the devices and plating solutions. In this research, the effects of levelers on copper electrodeposition were investigated without suppressor and accelerator to lower the concentration of additives. Threelevelers(janus green B, methylene violet, diazine black) were investigated to study the effects of levelers on copper deposition. Electrochemical behaviors of these levelers were different in terms of deposition rate. Filling performances were analyzed by cross sectional images and its characteristics were different with variations of levelers.