• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1611_1612
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• 2009

접합온도의 증가는 PN 접합 부분에서 생성된 열이 외부로 원활하게 방출되는 것을 저하시키고, 칩 내부에 남은 열이 전자와 정공의 비발광 재결합을 증가시켜 LED의 신뢰성과 내구성에 큰 영향을 미친다. 본 논문에서는 PMS-50과 KEITHLEY 2430을 이용하여 FR4 PCB의 Via hole 구성에 따른 LED 패키지의 열적 광학적 특성을 분석하였다. Via hole 0.6 [mm]일 때 열 특성과 광 출력 특성이 가장 우수하였으며 Via hole 1.2 [mm]는 열 특성, 광 특성이 가장 떨어졌고, 열 특성은 곧바로 광 특성에 영향을 미치는 것을 알 수 있었다.

• Transactions of Materials Processing
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• v.14 no.3 s.75
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• pp.277-281
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• 2005

LTCC(Low temperature co-fired ceramic) is being recognized as a significant packaging material of electrical devices for the advantages such as relatively low temperature being needed for process, low conductor resistance and high printing resolution. In the process of LTCC electrical devices, the punched via-hole quality is one of the most important factors on the performance of the device. However, its mechanism is very complicated and optimization of the process seems difficult. In this paper, to clarify the process, via-hole punching experiments were carried out and the punched holes were examined in terms of their burr formation. The effects of thickness of PET sheet, ceramic sheet and punch-to- die clearance on via-hole quality were also discussed. Optimum process conditions are proposed and a factor $\kappa$ is introduced to express effect of the process variables.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.39-43
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• 2012

Via-filling plating and through-hole plating are absolutely imperative for manufacturing of printed-wiring board. This Paper is introducing the latest developments of our company worked on the high-performance of acid copper plating additives for them.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.43-49
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• 2006

The properties, behavior and reliability of the residual void in blind via hole(BVH) were carried out for the shape of BVH using the void extraction process. The residual void was perfectly removed in the specimens applied by the void extraction process, which was improved by 40% rather than the conventional process. The residual void in BVH was to be eliminated under a condition of 1.5 atm for more 30 sec with regardless of the shape of BVH. It was also observed that the residual void in BVH was not formed after the reliability test with JEDEC standard.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.101-101
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• 2003

Al 박막의 화학증착(CVD)과 Al-Cu 합금박막의 물리증착(PVD)을 조합하는 CVD-PVD Al 공정은 수평방향의 배선과 수직방향의 via를 동시에 형성할 수 있으므로 공정단순화 및 생산원가절감 측면에서 장점이 있어서 DRAM 둥의 반도체 소자의 배선공정으로 매우 유망하다[1]. 본 연구에서는 CVD-PVD Al 공정을 이용하여 초고집적소자의 Al via와 Al 배선을 동시에 형성할 때 층간절연막의 영향을 조사하고 그 원인을 규명하였다. Al CVD를 위한 원료기체로는 dimethylaluminum hydride [($CH_3$)$_2$AlH]를 사용하였고 PVD는 38$0^{\circ}C$에서 실시하였다 층간절연막에 따른 CVD-PVD Al의 via hole 매립특성을 조사한 결과, high-density plasma(HDP) CVD oxide의 경우에는 via hole 매립특성이 우수하였으나, hydrogen silscsquioxane (HSQ)의 경우에는 매립특성이 우수하지 않아서 via 저항이 불균일 하였다. 이는 via 식각 후 wet cleaning 과정에서 HSQ에 흡수된 수분이 lamp를 이용한 degassing 공정에 의해서 완전히 제거되지 않아 CVD-PVD 공정 중에 탈착되어 Al reflow에 나쁜 영향을 미치기 때문으로 판단된다. CVD-PVD 공정 전에 40$0^{\circ}C$, $N_2$ 분위기에서 baking하여 HSQ 내의 수분을 충분히 제거함으로써 via 매립특성을 향상시킬 수 있었다. CVD-PVD Al 공정은 aspect ratio 10:1 이상의 via hole도 완벽하게 매립할 수 있었고 이에의해 제조된 Al 배선은 기존의 W plug 공정에 의해 제조된 배선에 비해 낮은 via 저항을 나타내었다.

• Journal of the Korean Society of Safety
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• v.27 no.6
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• pp.26-30
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• 2012

It is difficult to determine the junction temperature because LED lightings are manufactured using several chips with low power. This paper reports on the finite element method of the determination of junction temperature in the GaN-based LEDs. The calculated junction temperature of the LED chip using FEM was compared with the experimentally measured data. As the results of this study, the junction temperature of LED chips with via holes is lower than that of LED chips without via hole. Therefore, the research of via hole is necessary to decrease junction temperature of LED chips.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.244-250
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• 2008

An inductively coupled plasma etching process to replace an existing slower rate reactive ion etching process for $60{\mu}m$ diameter via-holes using Cl2/BCl3 gases has been investigated. Process pressure and platen power were varied at a constant ICP coil power to reproduce the RIE etched $200{\mu}m$ deep via profile, at high etch rate. Desired etch profile was obtained at 40 m Torr pressure, 950 W coil power, 90W platen power with an etch rate ${\sim}4{\mu}m$/min and via etch yield >90% over a 3-inch wafer, using $24{\mu}m$ thick photoresist mask. The etch uniformity and reproducibility obtained for the process were better than 4%. The metallized via-hole dc resistance measured was ${\sim}0.5{\Omega}$ and via inductance value measured was $\sim$83 pH.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.10a
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• pp.187-188
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• 2009

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2004.11a
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• pp.260-265
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• 2004

LTCC(Low temperature co-fired ceramic) is being recognized as a significant packaging material of electrical devices for the advantages such as relatively low temperature being needed for process, low conductor resistance and high printing resolution. In the process of LTCC electrical devices, the punched via-hole quality is one of the most important factors on the performance of the device. However, its mechanism is very complicated and optimization of the process seems difficult. In this paper, to clarify the process, via-hole punching experiments were carried out and the punched holes were examined in terms of their burr formation. The effects of thickness of PET sheet and ceramic sheet and punch-to-die clearance on via-hole quality were also discussed. Optimum process conditions are proposed and a factor k is introduced to express effect of the process variables.

• Journal of Advanced Navigation Technology
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• v.17 no.6
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• pp.658-663
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• 2013

In this paper, a microstrip line implementation using via transition and its application of multilayer compact ring hybrid coupler are presented. This transition is the sandwich structure with via hole to connect two microstrip lines in different layer. For designing a compact RF/Microwave passive circuit, the microstrip line using via-hole transition is proposed to reduce a size of microwave circuit with long transmission line. For the validation of the microstrip line with via-hole transition, the multilayer ring hybrid coupler is implemented at center frequency of 2 GHz. The measured performances are in good agreement with simulation results and about 50% size reduction compare to conventional ring hybrid coupler.