• 구강회복응용과학지
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• 제22권3호
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• pp.221-230
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• 2006

Recently, the need for esthetic results has increased the interest for all-ceramic crown prosthesis. Furthermore, the development of zirconium core via CAD/CAM system has allowed the all ceramic restorations to be applied to almost all fixed prosthesis situations. But, the increased strength has been reported to increase in proportion with the bond strength of cement, and recently, the tribochemical system which increases the bond strength through, silica coating and silanization has been introduced. The purpose of this study was to compare the $Rocatec^{TM}$ system and $CoJet^{TM}$ system with the traditional acid etching and silanization method of the irconium based ceramic. The surface character was observed via SEM(X2000), and the bond strength with the resin cement were measured. 50 In-Ceram Zirconia (Adens, Korea) discs were fabricated and embedded in resin, group 1 was treated with glass-bead blasting and cleaning, group 2 was treated with 20% HF for 10 minutes and silanized, group 3 was treated with the $Rocatec^{TM}$ system, and group 4 was treated with the $CoJet^{TM}$ system. Each group was comprised of 10 specimens. The specimens were cemented to a $3mm{\times}5mm$ resin block with Super-Bond C&B. The shear bond strength was measured with the $Instron^{(R)}$ 8871 at a crosshead speed of 0.5mm/min. The results were as follows. 1. According to SEM results, there were little difference between group 1 & group 2, but in group 3 and 4, silica coating was detected and there was increase in surface roughness. 2. The shear bond strength decreased in the order of group 3(46.28MPa), group 4(42.04MPa), group 2(31.56MPa), and group 1(27.46MPa). 3. There was significant differnce between group 1&2 and group 3&4(p<0.05). From the results above, it can be considered that the conventional method of acid etching and silane treatment cannot increase the bond strength with resin cements, and that by applying the tribochemical system of $Rocatec^{TM}$ system and $CoJet^{TM}$ system, we can achieve a stronger all ceramic restoration. Further studies on surface treatments to increase the bond strength are thought to be needed.

• 한국진공학회지
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• 제20권1호
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• pp.63-69
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• 2011

본 연구에서는 기존 실리콘 반도체 기술 기반의 포토 및 이빔 리소그래피 공정을 통하여 유기 반도체 소자를 패터닝하였다. P3HT나 PEDOT 등의 유기 반도체는 용매에 녹기 때문에 MIMIC (micro-molding in capillaries)이나 inkjet printing 기술을 이용하여 마이크로미터 크기의 소자 제작이 가능하였으나, 펜타신은 용매에 녹지 않기 때문에 매우 복잡한 방법으로 마이크로미터 크기의 소자를 제작하여왔다. 그러나, 본 연구에서는 원자층 증착 방법으로 증착한 산화 알루미늄막을 펜타신의 보호층으로 이용하여 기존의 포토 및 이빔 리소그래피 방법으로 마이크로미터크기의 펜타신 소자를 제작하였으며 그 전기 특성을 확인하였다.

• Journal of the Korean Association of Oral and Maxillofacial Surgeons
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• 제42권6호
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• pp.345-351
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• 2016

Objectives: This study compared the impact of implant surface treatment on the stability and osseointegration of implants in dog mandibles. Materials and Methods: Six adult dogs received a total of 48 implants that were prepared using four different surface treatments; resorbable blast media (RBM), hydroxyapatite (HA), hydrothermal-treated HA, and sand blasting and acid etching (SLA). Implants were installed, and dogs were separated into 2- and 4-week groups. Implant stability was evaluated via Periotest M, Osstell Mentor, and removal torque analyzers. A histomorphometric analysis was also performed. Results: The stability evaluation showed that all groups generally had satisfactory values. The histomorphometric evaluation via a light microscope revealed that the HA surface implant group had the highest ratio of new bone formation on the entire fixture. The hydrothermal-treated HA surface implant group showed a high ratio of bone-to-implant contact in the upper half of the implant area. Conclusion: The hydrothermal-treated HA implant improved the bone-to-implant contact ratio on the upper fixture, which increased the implant stability.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.523-523
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• 2012

As the wafer geometric requirements continuously complicated and minutes in tens of nanometers, the expectation of real-time add-on sensors for in-situ plasma process monitoring is rapidly increasing. Various industry applications, utilizing plasma impedance monitor (PIM) and optical emission spectroscopy (OES), on etch end point detection, etch chemistry investigation, health monitoring, fault detection and classification, and advanced process control are good examples. However, process monitoring in semiconductor manufacturing industry requires non-invasiveness. The hypothesis behind the optical monitoring of plasma induced ion current is for the monitoring of plasma induced charging damage in non-invasive optical way. In plasma dielectric via etching, the bombardment of reactive ions on exposed conductor patterns may induce electrical current. Induced electrical charge can further flow down to device level, and accumulated charges in the consecutive plasma processes during back-end metallization can create plasma induced charging damage to shift the threshold voltage of device. As a preliminary research for the hypothesis, we performed two phases experiment to measure the plasma induced current in etch environmental condition. We fabricated electrical test circuits to convert induced current to flickering frequency of LED output, and the flickering frequency was measured by high speed optical plasma monitoring system (OPMS) in 10 kHz. Current-frequency calibration was done in offline by applying stepwise current increase while LED flickering was measured. Once the performance of the test circuits was evaluated, a metal pad for collecting ion bombardment during plasma etch condition was placed inside etch chamber, and the LED output frequency was measured in real-time. It was successful to acquire high speed optical emission data acquisition in 10 kHz. Offline measurement with the test circuitry was satisfactory, and we are continuously investigating the potential of real-time in-situ plasma induce current measurement via OPMS.

• Bulletin of the Korean Chemical Society
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• 제35권1호
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• pp.35-38
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• 2014

Herein, we report on the preparation of red fluorescent Si nanoparticles stabilized with styrene. Nano-sized Si particles emit fluorescence under UV excitation, which could be used to open up new applications in the fields of optics and semi-conductor research. Unfortunately, conventional methods for the preparation of red fluorescent Si nanoparticles suffer from the lack of a fully-established standard synthesis protocol. A common initial approach during the preparation of semi-conductors is the etching of crystalline Si wafers in a HF/ethanol/$H_2O$ bath, which provides a uniformly-etched surface of nanopores amenable for further nano-sized modifications via tuning of various parameters. Subsequent sonication of the etched surface crumbles the pores on the wafer, resulting in the dispersion of particles into the solution. In this study, we use styrene to occupy these platforms to stabilize the surface. We determine that the liberated silicon particles in ethanol solution interact with styrene, resulting in the substitution of Si-H bonds with those of Si-C as determined via UV photo-catalysis. The synthesized styrene-coated Si nanoparticles exhibit a stable, bright, red fluorescence under excitation with a 365 nm UV light, and yield approximately 100 mg per wafer with a synthesis time of 2 h. We believe this protocol could be further expanded as a cost-effective and high-throughput standard method in the preparation of red fluorescent Si nanoparticles.

• 대한금속재료학회지
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• 제48권7호
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• 대한금속재료학회지
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• 제50권2호
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• pp.152-158
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• 2012

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• 센서학회지
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• 제22권1호
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• pp.89-94
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• 2013

In this paper, we developed a beam of MEMS probe card using a BeCu sheet. Silicon wafer thickness of $400{\mu}m$ was fabricated by using deep reactive ion etching (RIE) process. After forming through silicon via (TSV), the silicon wafer was bonded with BeCu sheet by soldering process. We made BeCu beam stress-free owing to removing internal stress by using joule heating. BeCu beam was fused by using joule heating caused by high current. The fabricated BeCu beam measured length of 1.75 mm and width of 0.44 mm, and thickness of $15{\mu}m$. We measured fusing current as a function of the cutting planes. Maximum current was 5.98 A at cutting plane of $150{\mu}m^2$. The proposed low-cost and simple fabrication process is applicable for producing MEMS probe beam.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2013년도 제44회 동계 정기학술대회 초록집
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• pp.618-618
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• 2013

Graphene is only one atom thick planar sheet of sp2-bonded carbon atoms arranged in a honeycomb crystal lattice, which has flexible and transparent characteristics with extremely high mobility. These noteworthy properties of graphene have given various applicable opportunities as electrode and/or channel for various flexible devices via suitable physical and chemical modifications. In this work, for the development of all-graphene devices, we performed to synthesize alternately patterned structure of mono- and multi-layer graphene by using the patterned Ni film on Cu foil, having much different carbon solid solubilities. Depending on the process temperature, Ni film thickness, introducing occasion of methane and gas ratio of CH4/H2, the thickness and width of the multi-layer graphene were considerably changed, while the formation of monolayer graphene on just Cu foil was not seriously influenced. Based on the alternately patterned structure of mono- and multi-layer graphene as a channel and electrode, respectively, the flexible TFT (thin film transistor) on SiO2/Si substrate was fabricated by simple transfer and O2 plasma etching process, and the I-V characteristics were measured. As comparing the change of resistance for bending radius and the stability for a various number of repeated bending, we could confirm that multi-layer graphene electrode is better than Au/Ti electrode for flexible applications.