• Proceedings of the KIEE Conference
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• 2008.10b
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• pp.165-168
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• 2008

The experimental results of exposing IGBT (Insulated Gate Bipolar Transistor) samples to gamma radiation source show shifting of threshold voltages in the MOSFET and degradation of carrier mobility and current gains. At low total dose rate, the shift of threshold voltage is the major contribution of current increases, but for more than some total dose, the current is increased because of the current gain degradation occurred in the vertical PNP at the output of the IGBTs. In the paper, the collector current characteristics as a function of gate emitter voltage (VGE) curves are tested and analyzed with the model considering the radiation damage on the devices for gate bias and different dose. In addition, the model parameters between simulations and experiments are found and studied.

• The Magazine of the IEIE
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• v.24 no.6
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• pp.38-49
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• 1997

0.4mm Resign Rule의 Super Low Power Dissipation, Low Voltage. Operation-5- Full CMOS SRAM Cell을 개발하였다. Retrograde Well과 PSL(Poly Spacer LOCOS) Isolation 공정을 사용하여 1.76mm의 n+/p+ Isolation을 구현하였으며 Ti/TiN Local Interconnection을 사용하여 Polycide수준의 Rs와 작은 Contact저항을 확보하였다. p-well내의 Boron이 Field oxide에 침적되어 n+/n-well Isolation이 취약해짐을 Simulation을 통해 확인할 수 있었으며, 기생 Lateral NPN Bipolar Transistor의 Latch Up 특성이 취약해 지는 n+/n-wellslze는 0.57mm이고, 기생 Vertical PNP Bipolar Transistor는 p+/p-well size 0.52mm까지 안정적인 Current Gain을 유지함을 알 수 있었다. Ti/TiN Local Interconnection의 Rs를 Polycide 수준으로 낮추는 것은 TiN deco시 Power를 증가시키고 Pressure를 감소시킴으로써 실현할 수 있었다. Static Noise Margin분석을 통해 Vcc 0.6V에서도 Cell의 동작 Margin이 있음을 확인할 수 있었으며, Load Device의 큰 전류로 Soft Error를 개선할수 있었다. 본 공정으로 제조한 1M Full CMOS SRAM에서 Low Vcc margin 1.0V, Stand-by current 1mA이하(Vcc=3.7V, 85℃기준) 를 얻을 수 있었다.

• Polymer(Korea)
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• v.30 no.3
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• pp.253-258
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• 2006

We have fabricated vortical type organic thin film transistors (OTFTs) consisting of ITO/n type active material/Al gate/n type active material/Al using F16CuPc, NTCDA, PTCDA and PTCDI C-8. The effect of mobility of n type active materials and thin film thickness on current-voltage (I-V) characteristics and on/off ratios were investigated. The vortical type organic transistor using PTCDI C-8 exhibited low operation voltage and high on-off ratio. In addition, we have investigated the feasibility of application in organic light emitting transistor using light emitting polymer. Especially, the light emitting transistor consisting of ITO/PEDOT-PSS/P3HT/F16CuPc/Al gate/F16CuPc/Al showed the maximum quantum efficiency of 0.054.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.9
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• pp.1627-1634
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• 2017

In this work, a junctionless transistor with different film thickness of amorphous InGaZnO has been fabricated and it's instability has been analyzed with different film thickness under positive and negative gate stress as well as light illumination. It was found that the threshold voltage shift and the variation of drain current have been increased with decrease of film thickness under the condition of gate stress and light illumination. The reasons for the observed results have been explained by stretched-exponential model and device simulation. Due to the reduced carrier trapping time with decrease of film thickness, electrons and holes can be activated easily. Due to the increase of vertical channel electric field reaching the back interface with decrease of film thickness, more electrons and holes can be accumulated in back interface. When one decides the film thickness for the fabrication of junctionless transistor, the more significant device instability with decrease of film thickness should be consdered.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.271-276
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• 2017

The triple-gate tunnel FETs encapsulated with an epitaxial layer (EL TFETs) is proposed to lower the subthreshold swing of the TFETs. Furthermore, the band-to-band tunneling based on the maximum electric-field can occur thanks to the epitaxial layer wrapping the Si fin. The performance and mechanism of the EL TFETs are compared with the previously proposed TFET based on simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.41-45
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• 2012

We observed that in chemical vapor deposition (CVD) tungsten silicide (WSix) poly gate scheme, the gate oxide thickness decreases as gate length is reduced, and it intensifies the roll-off properties of transistor. This is because the fluorine diffuses laterally from WSix to the gate sidewall oxide in addition to its vertical diffusion to the gate oxide during gate re-oxidation process. When the channel length is very small, the gate oxide thickness is further reduced due to a relative increase of the lateral diffusion than the vertical diffusion. In DRAM cells where the channel length is extremely small, we found the thinned gate oxide is a main cause of poor retention time.

• Journal of Information Display
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• v.1 no.1
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• pp.3-8
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• 2000

We have developed a high performance vertical alignment TFT-LCD (Thin Film Transistor Liquid Crystal Display), that shows a high light transmittance, and wide viewing angle characteristics with an unusually high contrast ratio. In order to optimize the electro-optical properties we have studied the effect of cell parameters, multi-domain structure and retardation film compensation. With the optimized cell parameters and process conditions, we have achieved a 24" wide UXGA TFTLCD monitor (16:10 aspect ratio 1920X1200) showing a contrast ratio of over 500:1, panel transmittance near 4.5%, response time near 25 ms, and viewing angle higher than 80 degree in all directions.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1440-1442
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• 2005

We have fabricated vertical type organic thin film transistors (OTFTs) using organic semiconductor materials such as F16CuPc, NTCDA, PTCDI C-8 and C60. The layers of OTFT were fabricated by vacuum evaporation technique and spin casting method onto the Indium Tin Oxide (ITO) coated glass. I-V characteristics and on-off ratios of the fabricated OTFTs were investigated. In addition, we have fabricated light emitting transistor using MEH-PPV and then investigated EL electroluminescent properties.

• Current Applied Physics
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• v.18 no.11
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• pp.1415-1421
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• 2018

Unlike ordinary organic field-effect transistors (OFETs), saturation current is hardly to be found in vertical OFETs (VOFETs). Moreover, the fabrication process of patterned sourced for VOFETs is quite complex. In this current work, a simple solution processed VOFET with directly deposited intermediate silver source electrode has been demonstrated. The VOFET exhibits a high leakage current that induces an inversion polarity of its transistor behavior. Interestingly, a well-defined saturation current was observed in the linear scale of transfer characteristic. The VOFET operated with high-current density > $280mA/cm^2$ at $V_d=5V$. Overview potential of the fabricated device in display application is also presented. This preliminary work does open-up a new direction in VOFET fabrication and their application.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.6
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• pp.773-779
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• 1986

In this paper, we discuss fabrication and characteristics of the Vertical Double diffused MOS(VDMOS) transistor. The epi layers of starting wafers are 18~22\ulcorner in thickness and 8~12\ulcornercm in resistivity. The channel regions are defined through the self-aligned double diffusion process. The characteristics of the fabricated VDMOS are breakdown voltage of 240V, threshold voltage of 2V, on-resistance of 226\ulcornerand transconductance of 3x10**-3 mho.