• 한국지반공학회:학술대회논문집
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• 한국지반공학회 1999년도 연약지반처리위원회 학술세미나
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• pp.62-70
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• 1999

Artesian pressure exists in Yangsan site, the maximum value of which has been measured as high as 5 t/m$^2$. This paper deals with the prediction of consolidation settlement for the site with artesian pressure. The consolidation settlement at the site has been accelerated using vertical band drains. Since the artesian pressure gives lower effective stress than a static condition, its effect should be considered in the settlement prediction. This case study shows that the prediction of settlement and pore pressure dissipation agrees well with the measurements, when considering the artesian effect.

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 2001년도 가을 학술발표회 논문집
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• pp.65-94
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• 2001

The use of PBD(prefabricated band drain)far ground improvement is rapidly increased due to the merit of construction period and cost, environmental preservation compared with other vertical drain method, and the development of material. This paper presents the historical review, theoretical background, design procedure and method, and typical construction example for the PBD. Also, the direction of further technical development and study is recommended.

• 한국지반공학회논문집
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• 제16권1호
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• pp.43-50
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• 2000

본 논문은 실내시험과 수치모델을 이용하여 십자형 배수재의 압밀촉진효과와 등가직경을 검토하고 판형배수재와 비교하였다. 배수재의 등가직경은 실내시험으로부터 역계산하여 문헌에 의해 제시된 공식으로부터 산정된 결과와 비교하였고, 압밀효과는 3차원 흐름해석프로그램인 MODFLOW를 사용하였다. 해석모델의 신뢰성은 현장의 침하-시간 계측자료를 이용하여 검토하였다. 실내시험결과 산정된 판형 배수재의 등가직경은 Rixner의 제안식에 유사한 경향을 보였고, 십자형 배수재의 등가직경은 $d_w\;=\; \\tarc{3}{4}.(b+t)$로 산정되었다. 실제현장을 모델링한 수치해석결과 십자형 배수재는 압밀시간이 9-10% 감소하였고, 현장자료를 이용한 수치 흐름모델로부터 산정한 등가직경은 실내시험보다 3.5배 작은 것으로 나타났다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권6호
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• pp.585-593
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• 2015

In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

• 센서학회지
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• 제29권4호
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• pp.275-278
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• 2020

In this study, we evaluated the temperature-dependent characteristics of homojunction InGaAs vertical Fin-shaped Tunnel Field-Effect Transistors (Fin TFETs), which were fabricated using a novel nano-fin patterning technique in which the Au electroplating and the high-temperature InGaAs dry-etching processes were combined. The fabricated homojunction InGaAs vertical Fin TFETs, with a fin width and gate length of 60 nm and 100 nm, respectively, exhibited excellent device characteristics, such as a minimum subthreshold swing of 80 mV/decade for drain voltage (V_DS) = 0.3 V at 300 K. We also analyzed the temperature-dependent characteristics of the fabricated TFETs and confirmed that the on-state characteristics were insensitive to temperature variations. From 77 K to 300 K, the subthreshold swing at gate voltage (V_GS) = threshold voltage (V_T), and it was constant at 115 mV/decade, thereby indicating that the conduction mechanism through band-to-band tunneling influenced the on-state characteristics of the devices.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.172-178
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• 2016

In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length ($L_{ch}$) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current ($I_{off}$) of $1.12{\times}10^{-11}A/{\mu}m$. In addition, the use of the highk spacer dielectric $HfO_2$ improves the on-state current ($I_{on}$) with an intrinsic delay time (${\tau}$) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower $I_{off}$ at a lower supply voltage ($V_{DD}$) of 0.2 V.