• Title/Summary/Keyword: Vertical band drain

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Consolidation Analysis of Vertical Drain Considering Artesian Pressure (피압수압을 고려한 연직배수공법의 압밀해석)

  • 김상규;김호일;홍병만;김현태
    • Proceedings of the Korean Geotechical Society Conference
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    • 1999.02a
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    • pp.62-70
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    • 1999
  • Artesian pressure exists in Yangsan site, the maximum value of which has been measured as high as 5 t/m$^2$. This paper deals with the prediction of consolidation settlement for the site with artesian pressure. The consolidation settlement at the site has been accelerated using vertical band drains. Since the artesian pressure gives lower effective stress than a static condition, its effect should be considered in the settlement prediction. This case study shows that the prediction of settlement and pore pressure dissipation agrees well with the measurements, when considering the artesian effect.

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한국에서의 PBD공법의 현황 및 문제점과 발전방향

  • 김영남;권성진
    • Proceedings of the Korean Geotechical Society Conference
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    • 2001.10a
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    • pp.65-94
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    • 2001
  • The use of PBD(prefabricated band drain)far ground improvement is rapidly increased due to the merit of construction period and cost, environmental preservation compared with other vertical drain method, and the development of material. This paper presents the historical review, theoretical background, design procedure and method, and typical construction example for the PBD. Also, the direction of further technical development and study is recommended.

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Estimation of Equivalent Diameter for Cross Shaped Vertical Drain Installed in Weak Clay Soils (연약점성토 지반에 타설된 십자형배수재의 등가직경 산정)

  • 장연수;김영우;김수삼
    • Journal of the Korean Geotechnical Society
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    • v.16 no.1
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    • pp.43-50
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    • 2000
  • In this paper, the consolidation efficiency and the equivalent diameter of the cross shaped drain are examined by using the laboratory test and the numerical model, and the results are compared with those of the band shaped drain. The equivalent diameter of the tested drains is back-calculated from the laboratory experiment and compared with those calculated from the formula suggested in the literature. The efficiency of the cross shaped drain is evaluated by using the 3-D flow program which was validated by the settlement-time test fill data. The results of laboratory test show that the equivalent diameter of the band shaped drain was close to the Rixner's formula and that of the cross shaped drain was fit to the following formula: $d_w\;=\; \\tarc{3}{4}.(b+t)$The results of the numerical analysis show that the cross shaped drain can reduce the consolidation time by 9-10% from that for the band shaped drain. The equivalent diameter obtained from the numerical flow model by using the field data is 3.5 times smaller than that obtained from the laboratory consolidation test.

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Triple Material Surrounding Gate (TMSG) Nanoscale Tunnel FET-Analytical Modeling and Simulation

  • Vanitha, P.;Balamurugan, N.B.;Priya, G. Lakshmi
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.585-593
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    • 2015
  • In the nanoscale regime, many multigate devices are explored to reduce their size further and to enhance their performance. In this paper, design of a novel device called, Triple Material Surrounding Gate Tunnel Field effect transistor (TMSGTFET) has been developed and proposed. The advantages of surrounding gate and tunnel FET are combined to form a new structure. The gate material surrounding the device is replaced by three gate materials of different work functions in order to curb the short channel effects. A 2-D analytical modeling of the surface potential, lateral electric field, vertical electric field and drain current of the device is done, and the results are discussed. A step up potential profile is obtained which screens the drain potential, thus reducing the drain control over the channel. This results in appreciable diminishing of short channel effects and hot carrier effects. The proposed model also shows improved ON current. The excellent device characteristics predicted by the model are validated using TCAD simulation, thus ensuring the accuracy of our model.

Temperature-dependent DC Characteristics of Homojunction InGaAs vertical Fin TFETs (동종 접합 InGaAs 수직형 Fin TFET의 온도 의존 DC 특성에 대한 연구)

  • Baek, Ji-Min;Kim, Dae-Hyun
    • Journal of Sensor Science and Technology
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    • v.29 no.4
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    • pp.275-278
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    • 2020
  • In this study, we evaluated the temperature-dependent characteristics of homojunction InGaAs vertical Fin-shaped Tunnel Field-Effect Transistors (Fin TFETs), which were fabricated using a novel nano-fin patterning technique in which the Au electroplating and the high-temperature InGaAs dry-etching processes were combined. The fabricated homojunction InGaAs vertical Fin TFETs, with a fin width and gate length of 60 nm and 100 nm, respectively, exhibited excellent device characteristics, such as a minimum subthreshold swing of 80 mV/decade for drain voltage (VDS) = 0.3 V at 300 K. We also analyzed the temperature-dependent characteristics of the fabricated TFETs and confirmed that the on-state characteristics were insensitive to temperature variations. From 77 K to 300 K, the subthreshold swing at gate voltage (VGS) = threshold voltage (VT), and it was constant at 115 mV/decade, thereby indicating that the conduction mechanism through band-to-band tunneling influenced the on-state characteristics of the devices.

Sub-10 nm Ge/GaAs Heterojunction-Based Tunneling Field-Effect Transistor with Vertical Tunneling Operation for Ultra-Low-Power Applications

  • Yoon, Young Jun;Seo, Jae Hwa;Cho, Seongjae;Kwon, Hyuck-In;Lee, Jung-Hee;Kang, In Man
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.2
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    • pp.172-178
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    • 2016
  • In this paper, we propose a sub-10 nm Ge/GaAs heterojunction-based tunneling field-effect transistor (TFET) with vertical band-to-band tunneling (BBT) operation for ultra-low-power (LP) applications. We design a stack structure that is based on the Ge/GaAs heterojunction to realize the vertical BBT operation. The use of vertical BBT operations in devices results in excellent subthreshold characteristics with a reduction in the drain-induced barrier thinning (DIBT) phenomenon. The proposed device with a channel length ($L_{ch}$) of 5 nm exhibits outstanding LP performance with a subthreshold swing (S) of 29.1 mV/dec and an off-state current ($I_{off}$) of $1.12{\times}10^{-11}A/{\mu}m$. In addition, the use of the highk spacer dielectric $HfO_2$ improves the on-state current ($I_{on}$) with an intrinsic delay time (${\tau}$) because of a higher fringing field. We demonstrate a sub-10 nm LP switching device that realizes a good S and lower $I_{off}$ at a lower supply voltage ($V_{DD}$) of 0.2 V.