• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.1
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• pp.35-46
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• 2004

In comparison with edge-emitting lasers(EELs), predicting the output power and slope efficiency of Vertical-Cavity Surface-Emitting Lasers(VCSELs) is very difficult due to the absorption loss in DBR layers. However, by using transfer matrix method(TMM), we've made possible to calculate such parameters of multi-layer structures like VCSELs. In this paper, we've calculated the threshold gain, threshold current and slope efficiency through the methodology based on TMM. Also TMM is the way of customizing the VCSEL structure for the desired threshold current and slope efficiency by changing the number of DBR mirror layers.

• Journal of Surface Science and Engineering
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• v.50 no.1
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• pp.10-16
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• 2017

This article reports for the first time on the lateral growth of PEO (plasma electrolytic oxidation) films on Al1050 alloy by the application of anodic pulse current in an alkaline electrolyte. Generation of microarcs was observed at the edges initially and then moved towards the central region with PEO treatment time. Disc type PEO film islands with about $20{\mu}m$ diameter were formed first and they grew laterally by the formation of new disc type PEO films at the edge of pre-formed PEO islands. The PEO film islands were found to be interconnected completely and form a continuous PEO film when generation of small size microarcs are terminated at the central part of the specimen, resulting in very smooth surface with low surface roughness less than $1{\mu}m$ of $R_a$. Further PEO treatment after the complete interconnection of PEO films islands showed local thickening of PEO films by vertical growth. It is concluded that very smooth PEO film surface can be obtained by lateral growth mechanism rather than vertical growth of them.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.1
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• pp.35-43
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• 2017

The three-dimensional integrated circuit (3D-IC) is a general trend for the miniaturized and high-performance electronic devices. The through-silicon-via (TSV) is the advanced interconnection method to achieve 3D integration, which uses vertical metal via through silicon substrate. However, the TSV based 3D-IC undergoes severe thermo-mechanical stress due to the CTE (coefficient of thermal expansion) mismatch between via and silicon. The thermo-mechanical stress induces mechanical failure on silicon and silicon-via interface, which reduces the device reliability. In this paper, the thermo-mechanical reliability of TSV based 3D-IC is reviewed in terms of mechanical fracture, heat conduction, and material characteristic. Furthermore, the state of the art via-level and package-level design techniques are introduced to improve the reliability of TSV based 3D-IC.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.570-572
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• 2012

In this paper, a three-dimensional (3-D) low-loss and wide-band BPF based on low-temperature co-fired ceramic (LTCC) has been presented for mm-wave wireless communication applications. The proposed BPF is designed in a 6-layer LTCC substrate. The double patch resonators are fully integrated into the LTCC dielectrics and vertical via and planar CPW transitions are designed for interconnection between embedded resonators and in/output ports and MMICs, respectively. The designed BPF was fabricated in a 6-layer LTCC dielectric. The fabricated BPF shows a centre frequency (fc) of 53.23 GHz and a 3dB bandwidth of 14.01 % from 49.5 to 56.9 GHz (7.46 GHz). An insertion loss of -1.56 dB at fc and return losses below -10 dB are achieved. Its whole size is $4.7{\times}1.7{\times}0.684mm^3$.

• 한국정보디스플레이학회:학술대회논문집
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• 2000.01a
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• pp.71-72
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• 2000

The design of large area thin film transistor liquid crystal displays (TFT-LCDs) requires consideration of cross-talks between the data lines and pixel electrodes. These limits are imposed by the mutual coupling capacitances present in a pixel. The mutual coupling capacitance causes a pixel voltage error. In this study, semi-empirical model, which is adopted from VLSI interconnection capacitance calculations, is used to calculate mutual coupling capacitances. With calculated mutual coupling capacitances and arbitrary given image pattern, the root mean square (RMS) voltage of pixel is calculated to see vertical cross-talk from the first to the last column. The information obtained this study can be utilized to design the larger area and finer image quality panel.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.2
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• pp.140-150
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• 1995

A symbolic layout generator, called Flexible Module Generator (FMG), has been developed for transgorming a given CMOS circuit netlist into an optimized symbolic layout. Contrary to other conventional module generators which place transistors either in horizontal or in vertical direction, FMG places transittors in any hence can multiples of 90$^{\circ}$. This flexible layout style can maximize the diffusion sharing and hence can reduce the wire-length for both of area minimization and performance improvement. In FMG, transistors are initially randomly placed and then selected transistors are iteratively replaced using an optimization technique based on simulated evolution. Whenever a transistor is replaced, the affected nets are rerouted. Constraints on the shape, aspect ratio, and critical path delays are considered during the optimization process. Routing is performed by using a modified maze router on polysilicon, metal 1, and metal 2 interconnection layers. additional routing grids are added, if necessary, for complete routing. Unused rows or columns are removed after routing for area minimization. Experimental reasults show that FMG synthesizes satisfactory layouts.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.557-560
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• 1999

The design of large area thin film transistor liquid crystal displays (TFT-LCDs) requires consideration of cross-talks between the data lines and pixel electrodes. These limits are imposed by the parasitic capacitive elements present in a pixel. The capacitive coupling of the data line signal onto the pixel causes a pixel voltage error. In this study semi-empirical capacitance model which is adopted from VLSI interconnection capacitance calculations was used to calculate mutual coupling capacitances. With calculated mutual coupling capacitances and given image pattern, the root mean square(RMS) voltage of pixel is calculated to see vertical cross-talk from the first to the last column. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Proceedings of the KIEE Conference
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• 1994.11a
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• pp.385-387
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• 1994

Optical interconnections are more attractive than electronic interconnections because of their higher speed, freedom from planar constraints, immunity to electromagnetic interference effects and higher interconnection capacity. Volume hologram is one of the best way to implement optical interconnections. Diffraction efficiency and crosstalk effect are very important things for ensuring independent interconnections. Recently, a general systematic method that can handle a large number of superposed volume gratings in anisotropic host material is presented. In this study for numerical analysis of diffraction, above method is programmed in general form near Bragg angle. Diffraction orders for variation of grating strength are determined by comparing with the coupled-mode method. The effects of parameter variation are considered. Parameters include vertical and azimuthal incident angle, wavelength and interaction length. Diffraction analyses are also performed for intra-mode and inter-mode diffractions.

• Proceedings of the Optical Society of Korea Conference
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• 1989.02a
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• pp.180-184
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• 1989

Overviews of vertical and horizontal GaAs/AlGaAs OEIC are shown. Researching double Zn diffusion process, we obtain Xj=At1/2-Bd1, where A=2.5${\mu}{\textrm}{m}$/[hr]1/2, B=0.625, of which process is recommended for exact diffusion interface area control of GaAs/AlGaAs. It is proved to be 100A/100A AlAs/GaAs using MOCVD by measurement of photo-luminescence which shows a luminescence peak corresponding to the 798.4nm wavelength calculated values of 38meV ground state above GaAs conduction band.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.112-117
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• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.