• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.05a
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• pp.757-759
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• 2013

Until just a few years ago, digital circuit design techniques in register transfer level using Verilog or VHDL have been recognized as the up-to-date way compared with the traditional schematic design, and truly they have been used as the most popular skill for most chip designs. However, with the advent of era in which the complexity of semiconductor chip counts over billion transistors with advanced manufacturing technology, designing in register transfer level became too complex to meet the requirements of the needs, so the design paradigm has to change so that both design and synthesis can be done in higher level of abstraction. Bluespec SystemVerilog (BSV) is the only HDL which enables both circuit design and generating synthesizable code in the system level developed so far. In this contribution, I survey and analyze the features which supports the new paradigm in the BSV HDL, not very familiar to industry yet.

• Journal of IKEEE
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• v.26 no.4
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• pp.577-583
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• 2022

Verilog-HDL-based modeling can be performed to confirm the fast operation characteristics after setting the design parameters of each block considering the stability of the system by performing linear phase-domain modeling on the phase-locked loop. This paper proposed Verilog-HDL modeling including DCO noise and DTC nonlinear characteristic. After completing the modeling, the time-domain transient simulation can be performed to check the feasibility and the functionality of the proposed PLL system, then the phase noise result from the system design based on the functional model can be verified comparing with the ideal phase noise graph. As a result of the comparison of simulation time (6 us), the Verilog-HDL-based modeling method (1.43 second) showed 484 times faster than the analog transistor level design (692 second) implemented by TSMC 0.18-㎛.

• Journal of Information Display
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• v.10 no.3
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• pp.101-106
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• 2009

In this study, a physical OLED analog behavior model for SPICE simulation was described using the Verilog-A language. The model was presented through theoretical equations for the J-V characteristics of OLED derived according to the internalcarrier emission equation based on a diffusion model at the Schottky barrier contact, and the mobility equation based on the Pool-Frenkel model. The accuracy of this model was examined by comparing it with the results of the device simulation that was conducted.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1212-1215
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• 2009

The theoretical equations for J-V characteristics in an OLED was derived according to the internal carrier emission equation based on a diffusion model at Schottky barrier contact and the mobility equation based on the Pool-Frenkel model. The J-V characteristics of OLED are presented using a behavioral model for analog systems (Verilog-A language), and the accuracy of this model was verified by comparing with the device simulation results.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.333-336
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• 2001

This paper describes the design and implementation results of 40, 32, 24 and 16kbps ADPCM encoder and decoder circuit, based on the protocol CCITT G.726. We verified the ADPCM algorithm using C language and designed the RTL circuit with Verilog HDL. The circuit has been simulated by Verilog-XL, synthesized by Design Compiler and verified using Xilinx FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in the digital voice and image processing SOC.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.728-732
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• 2014

Macro-model of magnetic tunnel junction (MTJ) for spin transfer torque magnetic random access memory (STT-MRAM) has been developed. The macro-model can describe the dynamic behavior such as the state change of MTJ as a function of the pulse width of driving current and voltage. The statistical behavior has been included in the model to represent the variation of the MTJ characteristic due to process variation. The macro-model has been developed in Verilog-A.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.852-855
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• 2003

This paper reports the RFC(Recursive Flow Classification) algorithm that is available on multiple fields. It is easy to be implemented by both software and hardware. For high speed classification of packets, the implementation of RFC is essential by hardware. Hence, in this paper, RFC algorithm is simulated by Verilog-HDL, and it verify the efficiency of the algorithm. The result shows that the algorithm can perform a packet classification within several cycles. It is not only much faster than software implementation but also enough to support OC192c.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.431-434
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• 2008

The physical OLED analog behavioral model for SPICE simulation has been described using Verilog-A language. The model is based on the carrier-balance between the hole and electron injected through Schottky barrier at anode and cathode. The accuracy of this model was examined by comparing with the results from device simulation.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.301-304
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• 2002

This paper describes the design and implementation results of JPEG core, based on the ITU-T Recommendation T.81. We designed the RTL circuit in Verilog HDL, making reference to the JPEG program from the Independent JPEG Group. The circuit has been simulated with Verilog-XL, synthesized with Design Compiler and verified using Altera FPGA. Since the synthesized circuit includes a small number of gates, it is expected to be used as a core module in image processing SOC.

• Journal of IKEEE
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• v.23 no.3
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• pp.800-804
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• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.