• ETRI Journal
• /
• v.43 no.2
• /
• pp.260-271
• /
• 2021

This paper addresses Very large-scale integration (VLSI) placement optimization, which is important because of the rapid development of VLSI design technologies. The goal of this study is to develop a hybrid algorithm for VLSI placement. The proposed algorithm includes a sequential combination of a genetic algorithm and an evolutionary algorithm. It is commonly known that local search algorithms, such as random forest, hill climbing, and variable neighborhoods, can be effectively applied to NP-hard problem-solving. They provide improved solutions, which are obtained after a global search. The scientific novelty of this research is based on the development of systems, principles, and methods for creating a hybrid (combined) placement algorithm. The principal difference in the proposed algorithm is that it obtains a set of alternative solutions in parallel and then selects the best one. Nonstandard genetic operators, based on problem knowledge, are used in the proposed algorithm. An investigational study shows an objective-function improvement of 13%. The time complexity of the hybrid placement algorithm is O(N2).

• Journal of the Institute of Convergence Signal Processing
• /
• v.3 no.1
• /
• pp.87-92
• /
• 2002

Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a stochastic evolution algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.8 no.1
• /
• pp.30-37
• /
• 1983

In this paper I have proposed a heuristic layout algorism which is important in the CAD system of VLSI. I have designed a placement algorism to be used the method which depends upon the synthetic judgment of human. The placement algorism can reflect the position of a module in a logical design circuit diagram drawn up by human beings. Also, in order to show the usefulness of the new method I have compared through a program experiment it with the former method of cluster development placement. Moreover, a routing algorism is proposed in order to reduce the excessive problem of memory capacity. Of course this new algorism compensates for the former Maze's defects.

• Journal of the Korea Society of Computer and Information
• /
• v.7 no.3
• /
• pp.42-48
• /
• 2002

Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

• Journal of the Institute of Convergence Signal Processing
• /
• v.4 no.4
• /
• pp.81-86
• /
• 2003

Current growth of VLSI design depends critically on the research and development of automatic layout tool. Automatic layout is composed of placement assigning a specific shape to a block and arranging the block on the layout surface and routing finding the interconnection of all the nets. Algorithms performing placement and routing impact on performance and area of VLSI design. Switchbox routing is a problem interconnecting each terminals on all four sides of the region, unlike channel routing. In this paper we propose a genetic algorithm searching solution space for switchbox routing problem. We compare the performance of proposed genetic algorithm(GA) for switchbox routing with that of other switchbox routing algorithm by analyzing the results of each implementation. Consequently experimental results show that out proposed algorithm reduce routing length and number of the via over the other switchbox routing algorithms.

• Journal of the Institute of Convergence Signal Processing
• /
• v.4 no.1
• /
• pp.64-70
• /
• 2003

Current growth of VLSI design depends critically on the research and development (If automatic layout tool. Automatic layout is composed of placement assigning a specific shape to a block and arranging the block on the layout surface and routing finding the interconnection of all the nets. Algorithms Performing placement and routing impact on Performance and area of VLSI design. Channel routing is a problem assigning each net to a track after global routing and minimizing the track that assigned each net. In this paper we propose a genetic algorithm searching solution space for the netlist partitioning problem for 4-layer channel routing. We compare the performance of proposed genetic algorithm(GA) for channel routing with that of simulated annealing(SA) algorithm by analyzing the results which are the solution of given problems. Consequently experimental results show that out proposed algorithm reduce area over the SA algorithm.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.10
• /
• pp.595-602
• /
• 2003

This Paper presents an efficient hybrid techniques for a standard cell placement. The prototype tool adopts a middle-down methodology in which an n${\times}$m grid is imposed over the layout area and cells are assigned to bins forming a global placement. The optimization technique applied in this phase is based on the Relaxation-Based Local Search (RBLS) framework [12］in which a combinatorial search mechanism is driven by an analytical engine. This enables a more global view of the problem and results in complex modifications of the placement in a single search“move.”Details of this approach including a novel placement legalization procedure are presented. When a global placement converges, a detailed placement is formed and further optimized by the optimal interleaving technique[13］. Experimental results on MCNC benchmarking circuits are presented and compared with the Feng Shui's results in［14］. Solution Qualifies are almost the same as the Feng Shui's results.

• 제어로봇시스템학회:학술대회논문집
• /
• 2005.06a
• /
• pp.1098-1100
• /
• 2005

The floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. And then, as the DSM advances, the VLSI chip becomes more congested even though more metal layers are used for routing. Usually, a VLSI chip includes several buses. As design increases in complexity, bus routing becomes a heavy task. To ease bus routing and avoid unnecessary iterations in physical design, we need to consider bus planning in early floorplanning stage. In this paper, we propose a floorplanning method for topological constraint consisting of bus constraint and memory constraint. The proposed algorithms based on Genetic Algorithm(GA) is adopted a sequence pair. For selection control, new objective functions are introduced for topological constraint. Studies on floor planning and cell placement have been reported as being applications of GA to the LSI layout problem. However, no studies have ever seen the effect of applying GA in consideration of topological constraint. Experimental results show improvement of bus and memory constraint.

• Journal of Electrical Engineering and information Science
• /
• v.3 no.3
• /
• pp.292-299
• /
• 1998

Placement of multiple dies on an MCM or high-performance VLSI substrate is a non-trivial task in which multiple criteria need to be considered simultaneously to obtain a true multi-objective optimization. Unfortunately, the exact physical attributes of a design are not known in the placement step until entire design process is carried out. When the performance issues are considered, crosstalk noise constraints in the form of net separation and via constraint become important. In this paper, for better performance and wirability estimation during placement for MCMs, several performance constraints are taken into account simultaneously. A graph-based wirability estimation along with the Genetic placement optimization technique is proposed to minimize crosstalk, crossing, wirelength and the number of layers. Our work is significant since it is the first attempt at bringing the crosstalk and other performance issues into the placement domain.

• Journal of KIISE:Computer Systems and Theory
• /
• v.29 no.6
• /
• pp.354-360
• /
• 2002

Delay estimation must be simple and efficient, since millions or more delay calculations may be required during a timing-driven placement stage. We have developed a new Modified Elmore delay estimation method, which is significantly more accurate than the original Elmore delay by considering resistance shielding effects, but has the same order of complexity with that of Elmore delay. Experimental results show that the suggested technique can significantly reduce the error in estimated delay, from 31.6 ~ 145.2% to 2.5 ~ 22.7%.