• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.5
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• pp.94-103
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• 1997

It is necesary that analog buffer circuit should drive an external load in the VLSI design such as switched capacitor efilter (SCF), D/A converter, A/d converter, telecommunicatin circuit, etc. The conventional CMOS buffer circuit have many probvlems according as CMOS technique. Firstly, Capacity of large load ar enot able to opeate well. The problem can be solve to use class AB stages. But large load are operated a difficult, because an element of existing CMOS has a quadratic functional relation with inptu and outut voltage versus output current. Secondly, whole circuit of dynamic rang edecrease, because a range of inpt and output voltages go down according as increasing of intergration rate drop supply voltage. In this paper suggests that new differential CMOS line driver make out of operating an external of large load. In telecommunication's chip case transmission line could be a load. It is necessary that a load operate line driver. The proposal circuit is planned to hav ea high generation power rnage of voltage with preservin linearity. And circuit of capability is inspected through simulation program (HSPICE).

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1998.06a
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• pp.756-761
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• 1998

This paper describes an in-line lossless data compression method using adaptive binary arithmetic coding. To achieve better compression efficiency , we employ an adaptive fuzzy -tuning modeler, which uses fuzzy inference to deal with the problem of conditional probability estimation. The design is simple, fast and suitable for VLSI implementation because we adopt the table -look-up approach. As compared with the out-comes of other lossless coding schemes, our results are good and satisfactory for various types of source data.

• The Journal of Korean Physical Therapy
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• v.13 no.2
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• pp.257-264
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• 2001

To take the Far-infrared(FIR) ray which is a optimized wavewlength and strength, at first, it is to be induced the characteristic algorithm and the computerized programing of FlR radiating materials. In this study, we induced that the formular of optimized FIR with physical, mathematical logic and theory, especially, Plank, Kirchhoff, Wien, Stefan-Boltzmann's logic and law. In the long run the formular was induced with mathematical integration. since we had to know the molecular wavelength. Base on the induced formular as above, we programmed the optimized FlR radiating computerized program, it would be useful to design semiconductor( VLSI) as the FlR instrument center control system.

• Journal of information and communication convergence engineering
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• v.9 no.3
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• pp.301-304
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• 2011

This paper describes the possibility of a low-power, high-resolution fingerprint sensor chip. A modified capacitive detection circuit of charge sharing scheme is proposed, which reduces the static power dissipation and increases the voltage difference between a ridge and valley more than conventional circuit. The detection circuit is designed and simulated in 3.3V, 0.35${\mu}$m standard CMOS process, 40MHz condition. The result shows about 27% power dissipation reduction and 90% improvement of difference between a ridge and valley sensing voltage. The proposed circuit is more stable and effective than a typical circuit.

• Proceedings of the Acoustical Society of Korea Conference
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• 1998.06c
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• pp.205-208
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• 1998

본 논문에서는 VLSI 기술에 바탕을 둔 top-down 접근 방식에 의하여 MPEG-2 오디오 부호화 알고리듬을 구현하였다. MPEG-2 오디오 부호화기의 알고리듬은 많은 연산량을 갖고 이질적인 특성을 갖고 이질적인 특성을 갖는 알고리듬들이 복합적으로 존재한다. 그러므로, 부호화기를 효과적으로 구현하기 위해서는 알고리듬 수준에서 구조적 수준에 이르기까지 많은 고찰이 이루어져야 한다. 본 논문에서는 우선 전체 부호화 알고리듬을 분석하여 이들을 다시 작업이라고 정의된 작은 부-알고리듬으로 나누었다. 다음으로, 분할된 작업들은 시간과 공간을 초대한 활용할 수 있도록 적절한 작업 순서를 부여하고, 좀 더 큰 모듈들로 모으는 클러스터링을 수행하였다. 마지막으로 이러한 분석 결과를 바탕으로, 실시간으로 동작하는 5.1 채널 MPEG-2 오디오 부호화기를 설계하였다. 설계된 시스템은 두 개의 하드웨어 블록과 한 개의 ASIP형 DSP 프로세서를 갖는 이질적인 다중 프로세서의 형태를 갖는다. 설계된 오디오 부호화기는 0.6$\mu\textrm{m}$ 표준 셀 기술을 이용하여 단일 칩으로 제작되었으며, PC에 탑재 가능한 시험 기판을 제작하여 동작을 검증하였다.

• Journal of Ocean Engineering and Technology
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• v.10 no.3
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• pp.162-167
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• 1996

This paper deals with an implementation method for the one chip microprocessor(8097)-based capacitance type wave recorder for a measuring real-time wave height. The system was developed to make it possible to real-time remote sensing the wave height by deploying the RS-232/422/485 communication methods. The system test results for the developed system such as linearity, system stability and robustness of the disturbance was also verified through the performance tests of the system. Furthermore, the system was developed after due consideration with connecting the public network such as satellite mobile communication system and LAN, through the deploying VLSI(Very Large Scale Integration) design techniques.

• Journal of Korean Institute of Industrial Engineers
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• v.21 no.1
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• pp.33-49
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• 1995

Simulated annealing(SA) has been admitted as a general purpose optimization technique which can be utilized for almost all kinds of combinatorial optimization problems without much difficulty. But there are still some weak points to be resolved, one of which is the slow speed of convergence. In this study, we carefully review various previous efforts to improve SA and propose some variations of SA which can enhance the speed of convergence to the optimum solution. Then, we apply the revised SA algorithms to the scheduling and hardware allocation problems occurring in high-level synthesis(HLS) of VLSI design. We confirm the efficiency of the proposed methods through several HLS examples.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.51-51
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• 2001

본 논문에서는 CMOS 로직과 pass-transistor logic(PTL)의 장점만을 가진 새로운 복합모드로직(Compound Mode Logic)을 제안하였다. 제안된 로직은 VLSI설계에서 중요하게 부각되고 있는 저전력, 고속 동작이 가능하며 실제로 전가산기를 설계하여 측정 한 결과 복합모드 로직의 power-delay 곱은 일반적인 CMOS로직에 비해 약 22% 개선되었다 제안한 복합모드 로직을 이용하여 고성능 32×32-bit 곱셈기를 설계 제작하였다. 본 논문의 곱셈기는 개선된 사인선택(Sign Select) Booth 인코더, 4-2 및 9-2 압축기로 구성된 데이터 압축 블록, 그리고 carry 생성 블록을 분리한 64-bit 조건 합 가산기로 구성되어 있다. 0.6um 1-poly 3-metal CMOS 공정을 이용하여 제작된 32×32-bit 곱셈기는 28,732개의 트랜지스터와 1.59×l.68 ㎜2의 면적을 가졌다. 측정 결과 32×32-bit 곱셈기의 곱셈시간은 9.8㎱ 이었으며, 3.3V 전원 전압에서 186㎽의 전력 소모를 하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2966-2977
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• 1996

As design of very large circuits is made possible by rapid development of VLSI technologies, efficient fault simulation is needed. Ingeneral, fault simulation requires many computer resources. As general-purpose multiprocessors become more common and affordable, these seem to be an attractive and effective alternative for fault simulation. Efficient fault simulation of synchronous sequential circuits has been reported to be attainably by using a linear iterative array model for such a circuit, and combining parallel fault simulation with russogate fault simulation. Such fault simulation algorithm is parallelized on a general-purpose multiprocessor with shard memory for acceleration of fault simulation. Through the experimenal study, the effect of the number of processors on speed-up of simulation, processor utilization, and the effect of multiprocessor hardware on simulation performance are studied. Some results for experiments with benchmark circuits are shown.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.453-454
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• 2008

Modern VLSI designs get increasingly complex and time-to-market constraints get tighter. Using high level languages is one of the most promising solutions for improving design productivity by raising the level of abstraction. In high level synthesis process, most important step is scheduling. In this paper, we propose fast and efficient scheduling method under timing constraint based on list scheduling. Experimental results on well known data path intensive designs show fast execution times (less than 0.5 sec) and similar results when compared to optimal solutions [1].