• 대한전자공학회논문지
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• 제21권5호
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• pp.61-66
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• 1984

C 언어로 만든 VLSI 레이아웃 언어를 사용하여 CMOS PLA를 설계한다. PLA cell의 library를 만들고 Protector 회로의 제어논리로 사용되는 PLA를 NCR 설계법칙을 이용하여 설계하고 레이아웃 프로그램을 만든다. 관련되는 프로그램 기법을 논의하고 레이아웃을 display할 수 있도록 한다.

• 전자공학회논문지A
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• 제30A권12호
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• pp.88-97
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• 1993

Electrostatic Discharge(ESD) is one of the major reliability, issues for today's VLSI production. Since the gate oxide with a thickness of 100~300$\AA$ is vulnerable to several thousand volt of ESD surge, it is necessary to control the ESD events and design an efficient protection circuit. In this paper, physical mechanism of the catastrophic ESD damage is investigated by transient analysis based upon Human Body Model(HBM). Using two-dimensional electrothermal simulator, we study the failure mechanism of the output protection devices by ESD and discuss the design issues for the optimun protection network.

• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2001년도 가을 학술발표논문집 Vol.28 No.2 (1)
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• pp.586-588
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• 2001

회로분할 기법은 VLSI 설계뿐만 아니라 많은 분야에서 응용될 수 있어 오랫동안 연구가 행해졌다. 대부분의 회로분할 휴리스틱에서 Fiduccia-Mattheyses(FM) 방법을 핵심 기술로 사용하고 있다. 회로 분할 문제는 또한 다른 컴비네토리얼 문제에서처럼 해 공간에서 최적해를 찾는 문제로 볼 수 있는데. GWW(Go With the Winners) 방법은 해 공간을 검색하는 성공적인 패러다임 중의 하나이다. 본 논문에서는 “GWW” 패러다임을 FM 방법에 접목시켜 회로를 분할하기 위한 휴리스틱을 제안한다. MCNC 벤치마크 회로를 이용하여 전형적인 FM 방법에 의한 결과와 “GWW”패러다임을 접목하여 얻은 결과를 비교하였다. 실험결과는 매우 고무적이다.

• 대한전자공학회논문지
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• 제27권12호
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• pp.1878-1888
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• 1990

In this paper, the input-output interconnection method of the multi-valued signal processing circuit using perfect Shuffle technique and Kronecker product is discussed. Using this method, the design method of circuit of the multi-valued Reed-Muller expansions(MRME) to be used the multi-valued signal processing on finite field GF(p**m) is presented. The proposed input-output interconnection method is shown that the matrix transform is efficient and that the module structure is easy. The circuit design of MRME on FG(p**m) is realized following as` 1) contructing the baisc gates on GF(3) by CMOS T gate, 2) designing the basic cells to be implemented the transform and inverse transform matrix of MRME using these basic gates, 3) interconnecting these cells by the input-output interconnecting method of the multivalued signal processing circuits. Also, the circuit design of the multi-valued signal processing function on GF(3\ulcorner similar to Winograd algorithm of 3x3 array of DFT (discrete fourier transform) is realized by interconnection of Perfect Shuffle technique and Kronecker product. The presented multi-valued signal processing circuits that are simple and regular for wire routing and posses the properties of concurrency and modularity are suitable for VLSI.

• 디지털산업정보학회논문지
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• 제19권2호
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• pp.11-25
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• 2023

With the increasing advancement of VLSI technology, health care system is also developing to serve the humanity with better care. Therefore, biomedical implantable devices are one of the amazing important invention of scientist to collect data from the body cell for the diagnosis of diseases without any pain. This Biomedical implantable transceiver circuit has several important issues. Oscillator is one of them. For the design flexibility and complete transistor-based architecture ring oscillator is favorite to the oscillator circuit designer. This paper represents the design and analysis of the a 9-stage CMOS ring oscillator using cadence virtuoso tool in 180nm technology. It is also designed to generate the carrier signal of 403.5MHz frequency. Ring oscillator comprises of odd number of stages with a feedback circuit forming a closed loop. This circuit was designed with 9-stages of delay inverter and simulated for various parameters such as delay, phase noise or jitter and power consumption. The average power consumption for this oscillator is 9.32㎼ and average phase noise is only -86 dBc/Hz with the source voltage of 0.8827V.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권4호
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• pp.477-483
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• 2015

The k-Winners-Take-All (kWTA) is an operation to find the largest k (>1) inputs among N inputs. Parallel search algorithm of kWTA for digital inputs is not invented yet, so most of digital kWTA architectures have O(N) time complexity. A parallel search algorithm for digital kWTA operation and the circuits for its VLSI implementation are presented in this paper. The proposed kWTA architecture can compare all inputs simultaneously in parallel. The time complexity of the new architecture is O(logN), so that it is scalable to a large number of digital data. The high-speed kWTA operation and its O(logN) dependency of the new architecture are verified by simulations. It takes 290 ns in searching for 5 winners among 1024 of 32 bit data, which is more than thousands of times faster than existing digital kWTA circuits, as well as existing analog kWTA circuits.

• 전자공학회논문지C
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• 제34C권8호
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• pp.8-21
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• 1997

In this paper, we consider resistive shorts on gate-source, gate-drain, and drain-source as well as opens in MOS FETs included in typical memory cell of VLSI SRAM and analyze behavior of memory by using PSPICE simulation. Using conventional fault models and this behavioral analysis, we propose linear testing algorithm of complexity O(N) which can be applied to both functional testing and IDDQ (quiescent power supply current) testing simultaneously to improve functionality and reliability of memory. Finally, we implement BIST (built-in self tsst) circuit and BICS(built-in current sensor), which are embedded on memory chip, to carry out functional testing efficiently and to detect various defects at high-speed respectively.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2007년도 추계학술대회 논문집
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• pp.356-359
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• 2007

Continuing improvements in integrated circuit chip density and functionality have mostly contributed toward a very large-scale integrated circuit(VLSI) and display device. In order to test (pass or fail) all of the high integrated semiconductor chip and display device, fine pitch probes are used. Fine pitch probes are manufactured by electroforming process of a Ni alloy in an electrolytic bath. In this paper, we expect that the electric field in bath with the Finite Element Method and applying the FEM result. So, we can obtained the probes that have high aspect ratio of 10 : 1

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 B
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• pp.1067.1-1067.4
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• 2000

During the last three decades power electronics has gone through energetic technical evolution. The technical needs from wide area such as in industrial, commercial, consumer, aerospace and environmental applications have driven the environment favorably for the power electronics. In the future, two extreme technology-expansion trends are expected: one into low power, and the other into very high power. The former is based on the high frequency and the circuit miniature using VLSI circuit and surface mounting aiming for the system-on-chip (SOC) technology. The latter includes the application areas of power utility such as HVDC, FACTS and SVC and large science area of electrophsycal apparatus such as thermonuclear fusion, acclerators, and electric guns. This paper describes the technology status of some major elements which are available today and the key roles of the power electronics from view points of applications. The author would like to take this opportunity to raise discussions about the future technology development trend of power electronics in our country with the fellow power electronics engineers.

• ETRI Journal
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• 제36권4호
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• pp.643-653
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• 2014

To reduce interconnect delay and power consumption while improving chip performance, a three-dimensional integrated circuit (3D IC) has been developed with die-stacking and through-silicon via (TSV) techniques. The power supply problem is one of the essential challenges in 3D IC design because IR-drop caused by insufficient supply voltage in a 3D chip reduces the chip performance. In particular, power bumps and TSVs are placed to minimize IR-drop in a 3D power delivery network. In this paper, we propose a design methodology for 3D power delivery networks to minimize the number of power bumps and TSVs with optimum mesh structure and distribute voltage variation more uniformly by shifting the locations of power bumps and TSVs while satisfying IR-drop constraint. Simulation results show that our method can reduce the voltage variation by 29.7% on average while reducing the number of power bumps and TSVs by 76.2% and 15.4%, respectively.