• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.7C
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• pp.540-547
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• 2008

In this paper, we proposed a new VLSI architecture which can generate computer-generated hologram (CGH) in real-time and implemented to hardware. The modified algorithm for high-performance CGH was introduced and re-analyzed (or designing hardware. from both numerical and visual analysis, the infernal number system of hardware was decided. CGH algorithm and precision analysis enabled to propose a new cell architecture for CGH. The operational sequence was analyzed with the architecture of CGH cell and the characteristics of the modified CGH algorithm, and finally the pipelined architecture and the operational timing were proposed.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.1
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• pp.42-46
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• 2010

Encapsulation for information security is often carried out in Galois field in the form of arithmetic operations. This paper proposes how to efficiently perform exponentiation of arithmetic information on Galois field. Especially, by improving an existing bit-parallel exponentiator to exclude elements with heavy gate counts and to take advantage of system constants, this paper proposes how to implement a VLSI architecture with high performance even for large m.

• Proceedings of the Acoustical Society of Korea Conference
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• 1994.06c
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• pp.399-402
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• 1994

본 논문에서는 국내에서 개발된 신경망 VLSI 인 URAN에 대하여 살펴보고 URAN을 이요한 DAM성 인식 시스템의 설계에 관해 기술한다. 시뮬레이션을 통해 낮은 정밀도의 입출력 및 연결강도, 선형 출력함수를 가지는 뉴런을 사용하는 신경망 음성 인식 시스템의 성능을 분석하고 잡음 환경에서 낮은 정밀도를 사용한 신경망의 성능 저하 정도를 검토한다.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.419-420
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• 2000

This paper describes the innovation of VLSI design methodology in the coming decade. Technology trend of VLSI fabrication is surveyed first. Then the so-called “design crisis” is analyzed. Finally, possible design methodology to overcome the design crisis is discussed.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.100-100
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• 2004

• The Journal of Natural Sciences
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• v.7
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• pp.27-35
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• 1995

This paper introduces a VLSI (Very Large Scale Integrated Circuit) implementation of the 2-D Discrete Cosine Transform (DCT) with an application to image and video coding. This implementation, which is based upon a state space model, uses both algorithm and data partitioning to achieve high efficiency. With this implementation, the amount of data transfers between the processing elements (PEs) are reduced and all the data transfers are limitted to be local. This system accepts the input as a progressively scanned data stream which reduces the hardware required for the input data control module. With proper ordering of computations, a matrix transposition between two matrix by matrix multiplications, which is required in many 2-D DCT systems based upon a row-column decomposition, can be also removed. The new implementation scheme makes it feasible to implement a single 2-D DCT VLSI chip which can be easily expanded for a larger 2-D DCT by cascading these chips.

• The Magazine of the IEIE
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• v.25 no.5
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• pp.31-41
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• 1998

With the advent of portable electronic systems, power consumption has recently become a major issue in circuit and system design. Furthermore, the sophisticated fabrication technology makes it possible to embed more functions and features in a VLSI chip, consequently calling for both higher performance and lower power to deal with the ever growing complexity of system algorithms than in the past. VLSI designers should cope with two conflicting constraints, high performance and low power, offering an optimum trade off of these constraints to meet requirements of system. Historically, VLSI designers have focused on performance improvement, and power dissipation was not a design criteria but an afterthought. This design paradigm should be changed, as power is emerging as the most critical design constraint. In VLSI design, low power design can be accomplished through many ways, for instance, process, circuit/logic design, architectural design, and etc.. In this paper, a few low power design examples, which have been used in 8 bit micro-controller core, and can be used also in 4/16/32 bit micro-controller cores, are presented in the areas of circuit, logic and architectural design. We first propose a low power guidelines for micro-controller design in SAMSUNG, and more detailed design examples are followed applying 4 specific design guidelines. The 1st example shows the power reduction through reduction of number of state clocks per instruction. The 2nd example realized the power reduction by applying RISC(Reduced Instruction Set Computer) concept. The 3rd example is to optimize the algorithm for ALU(Arithmetic Logic Unit) to lower the power consumption, Lastly, circuit cells designed for low power are described.

• The Transactions of the Korea Information Processing Society
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• v.4 no.6
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• pp.1495-1507
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• 1997

Among a number of approaches to text compression, adaptive dictionary schemes based on a sliding window have been very frequently used due to their high performance. The LZ77 algorithm is the most efficient algorithm which implements such adaptive schemes for the practical use of text compression. This paperpresents a VLSI architecture designed for processing the LZ77 algorithm in parallel. Compared with the other VLSI architectures developed so far, the proposed architecture provides the more viable solution to high performance with regard to its throughput, efficient implementation of the VLSI systolic arrays, and hardware scalability. Indeed, without being affected by the size of the sliding window, our system has the complexity of O(N) for both the compression and decompression and also requires small wafer area, where N is the size of the input text.

• 전자공학회논문지 IE
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• v.46 no.3
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• pp.26-32
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• 2009

The reason of the contamination in the VLSI industry is the electric charge of the wafer itself. We develop the corona discharged system of clearing static electricity with a fan. This system has automatic cleaner of discharging electrode, check the state of jot control a suitable mount of discharged ion, and monitor all state using Zigbee communication module.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.8 no.1
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• pp.30-37
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• 1983

In this paper I have proposed a heuristic layout algorism which is important in the CAD system of VLSI. I have designed a placement algorism to be used the method which depends upon the synthetic judgment of human. The placement algorism can reflect the position of a module in a logical design circuit diagram drawn up by human beings. Also, in order to show the usefulness of the new method I have compared through a program experiment it with the former method of cluster development placement. Moreover, a routing algorism is proposed in order to reduce the excessive problem of memory capacity. Of course this new algorism compensates for the former Maze's defects.