• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1021-1024
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• 1998

Computer-aided design of VLSI circuits is usually carried out in three synthesis steps; high-level synthesis, logic synthesis and layout synthesis. Each synthesis step is further kroken into a few optimization problems. In this paper we study the area minimization problem in floorplanning(also known as the floorplan sizing problem). We propose the area minimization algorithms for general floorplans.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1280-1283
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• 2002

This paper discusses issues in VLSI design and implementation of high performance datapath circuits. Of particular concern will he various types of multiplier and adder, which are fundamental to DSP operations. Performance comparison will be provided in terms of sampling speed, layout area, and in particular, power consumption, with techniques that may be applied to reduce power dissipation also suggested. As an example, a low power, high performance recursive filter achieved through bit-level pipelining technique is illustrated

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.329-332
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• 2001

This paper proposes a capacitance extraction algorithm based on boundary element method and describes the implemented 2-dimension extractor based on the proposed algorithm. The proposed algorithm uses a generalized conjugate residual iterative algorithm with a hierarchical subdivision. The implemented 2-D extractor computes the capacitances of complicated 2-D geometry of ideal conductors in uniform dielectric and can be efficiently used in the VLSI layout designs due to its user-friendly GUI.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.5
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• pp.61-66
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• 1984

In this paper a custom design of CMOS PLA using procedual language, CHISEL is presented. Library of cells of PLA pieces are formed. A typical PLA is used as a control logic for the protector circuit. NCR's design rules are applied to program CMOS PLA using CHISEL which is a VILI layout language made by extending C language.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.292-301
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• 2001

IDDQ Testing is a very effective testing method to detect many kinds of physical defects occurred in CMOS VLSI circuits. In this paper, we consider the most commonly occurring bridging faults in current CMOS technologies and develop pattern generator for IDDQ testing using efficient IDDQ test algorithms. The complete set of bridging faults between every pair of all nodes(internal and external nodes) within circuit under test is assumed as target fault model. The merit of considering the complete bridging fault set is that layout information is not necessary. Implemented test pattern generator uses a new neighbor searching algorithm and fault collapsing schemes to achieve fast run time, high fault coverage, and compact test sets. Experimental results for ISCAS benchmark circuits demonstrate higher efficiency than those of previous methods.

• Journal of information and communication convergence engineering
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• v.19 no.2
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• pp.114-119
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• 2021

This paper proposes a method to find an optimal T' with the most terminal of the subset of T' trees that can be connected by a given length by improving a memetic genetic algorithm within several constraints, when the set of terminal T is given to the Euclidean plane R². Constraint (1) is that a given length cannot connect all terminals of T, and (2) considers only the rectilinear layout of the edge connecting each terminal. The construction of interconnections has been used in various design-related areas, from network to architecture. Among these areas, there are cases where only the rectilinear layout is considered, such as wiring paths in the computer network and VLSI design, network design, and circuit connection length estimation in standard cell deployment. Therefore, the heuristics proposed in this paper are expected to provide various cost savings in the rectilinear layout.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.10
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• pp.595-602
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• 2003

This Paper presents an efficient hybrid techniques for a standard cell placement. The prototype tool adopts a middle-down methodology in which an n${\times}$m grid is imposed over the layout area and cells are assigned to bins forming a global placement. The optimization technique applied in this phase is based on the Relaxation-Based Local Search (RBLS) framework [12］in which a combinatorial search mechanism is driven by an analytical engine. This enables a more global view of the problem and results in complex modifications of the placement in a single search“move.”Details of this approach including a novel placement legalization procedure are presented. When a global placement converges, a detailed placement is formed and further optimized by the optimal interleaving technique[13］. Experimental results on MCNC benchmarking circuits are presented and compared with the Feng Shui's results in［14］. Solution Qualifies are almost the same as the Feng Shui's results.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1121-1124
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• 2002

In this paper, an IC realization of a cell-network type SC DC-DC converter is reported. To achieve small and low-cost realization, the converter is designed by using a 1.2 $\mu\textrm{m}$ CMOS technology. The CMOS implemented converter will be useful as a building block of various mobile equipments since step-up and step-down voltages can be provided at one time. Concerning the proposed DC-DC converter, SPICE simulatiorls are performed to investigate the characteristics of the circuit. The SPICE simulations show that, the efficiency of the simulated circuit is more than 95 %. From the layout design using a CAD tool, MAGIC, the VLSI chip is fabricated in the chip fabrication program of VLSI Design and Education Center(VDEC), the University of Tokyo with the collaboration by On-Semiconductor. The proposed circuit is integrable by a standard 1.2 $\mu\textrm{m}$ CMOS technology.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.514-523
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• 2006

In this paper we propose an extended interleaving technique to improve a detailed placement. The existing row-based interleaving technique allows cells to move only within a row and it can be applied when there is no space between cells. The proposed extended-interleaving technique releases such constraints so that cells can move along with a vertical line parallel to a y-axis and space between cells is properly handled. Converged detailed-placements by a mature CAD tool have been improved by the proposed interleaving technique by 9.5% on average in half-perimeter wire length.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.228-234
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• 2006

This paper describes a systematic process which can generate a complete circuit specification efficiently for a given recursive DSP algorithm based on an optimal multiprocessor scheduler. The process is composed of two states: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph(FSFG) as an input, and generates an optimal synchronous multiprocessor schedule. Then the circuit synthesis part translates the modified schedule into a complete circuit diagram including a control specification. The circuit diagram can be applied to a silicon compiler for VLSI layout generation. This paper illustrates the whole process with an example of a second order Gray-Market lattice filter.