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An Extended Interleaving Technique for Detailed Placement  

Oh Eun-Kyung (동아대학교 컴퓨터공학과)
Hur Sung-Woo (동아대학교 전자컴퓨터공학부)
Publication Information
Journal of KIISE:Computer Systems and Theory / v.33, no.8, 2006 , pp. 514-523 More about this Journal
Abstract
In this paper we propose an extended interleaving technique to improve a detailed placement. The existing row-based interleaving technique allows cells to move only within a row and it can be applied when there is no space between cells. The proposed extended-interleaving technique releases such constraints so that cells can move along with a vertical line parallel to a y-axis and space between cells is properly handled. Converged detailed-placements by a mature CAD tool have been improved by the proposed interleaving technique by 9.5% on average in half-perimeter wire length.
Keywords
VLSI Layout; Standard Cell; Placement; Dynamic Programming; Interleaving Technique;
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