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Implementation of Recursive DSP Algorithms Based on an Optimal Multiprocessor Scheduler  

Kim Hyeong-Kyo (한신대학교 정보통신학과)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.10, no.2, 2006 , pp. 228-234 More about this Journal
Abstract
This paper describes a systematic process which can generate a complete circuit specification efficiently for a given recursive DSP algorithm based on an optimal multiprocessor scheduler. The process is composed of two states: scheduling and circuit synthesis. The scheduling part accepts a fully specified flow graph(FSFG) as an input, and generates an optimal synchronous multiprocessor schedule. Then the circuit synthesis part translates the modified schedule into a complete circuit diagram including a control specification. The circuit diagram can be applied to a silicon compiler for VLSI layout generation. This paper illustrates the whole process with an example of a second order Gray-Market lattice filter.
Keywords
DSP; design synthesis system; multiprocessor scheduler; FSFG; Silicon compiler; Gray-Market Lattice later;
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