• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.7 no.3
• /
• pp.558-567
• /
• 2003

Most digital signal processors provide 4 external interrupt input channels. But these are not sufficient for external interrupts of motor controls. Customized programmable interrupt controller, 8259, has 8 interrupt channels. Therefore, in the case of more external interrupt channels are needed, designers must expand by cascading the 8259. And this, 8259 device, have some inconvenience of interfacing the microprocessor in motor controls. In this paper, the expanded interrupt controller with 14 sufficient interrupt input channels for motor controls is designed using VHDL on the purpose of interfacing the microprocessor to the interrupt controller more compatibly and increasing the device utilization of FPGA/CPLD designed another peripherals. The interrupt controller model and each function blocks is proposed and illustrated. Simulation result are presented to estimate the designed interrupt controller.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.18 no.5
• /
• pp.229-235
• /
• 2018

As of in the year of 2016, 40 million ARM processors are being shipped everyday and more than 86 billion ARM processors are mounted in mobile communications, consumer electronics, enterprises, and embedded systems. Nationally, we are capable of designing high-end memory semiconductors, but not in processors, resulting in unbalance. Generally, highly expensive software programs are necessary for designing processors which makes it difficult to set up proper environments. However, ModelSim simulator provided by Altera is free and everybody can use it. In this paper, the VHDL language which is widely used in Europe, universities, and research centers around the world for the ASIC design is selected for designing 32-bit ARM processor and simulated by ModelSim. As a result, 37 instructions of ARMv4 has been successfully executed.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.11C
• /
• pp.1107-1119
• /
• 2006

Data transmission experiences multiplicative distortion in frequency nonselective fading channel. This distortion occurs in OFDM communication channel and can be compensated using an equalizer. Usually, in the case of LMS equalizer, eigenvalue distribution of training signal is enlarged. Large eigenvalue distribution causes principally the performance of a communication system to be deteriorated. This paper proposes a new algorithm that shows the same performance as the existing fast wavelet transform algorithm with less computational complexity. The proposed algorithm was applied to an adaptive equalizer of OFDM communication system. Matlab simulation results show a better performance than the existing one. The proposed algorithm was implemented in VHDL and simulated.

• Journal of KIISE:Computing Practices and Letters
• /
• v.8 no.6
• /
• pp.717-726
• /
• 2002

In this study, we analyze hardware implementation schemes of the ARS(Advanced Encryption Standard-128) algorithm that has recently been selected as the standard cypher algorithm by NIST(National Institute of Standards and Technology) . The implementation schemes include the basic architecture, loop unrolling, inner-round pipelining, outer-round pipelining and resource sharing of the S-box. We used MaxPlus2 9.64 for VHDL design and simulations and FLEX10KE-family FPGAs produced by Altera Corp. for implementations. According to the results, the four-stage inner-round pipelining scheme shows the best performance vs. cost ratio, whereas the loop unrolling scheme shows the worst.

• Proceedings of the Korean Institute of Intelligent Systems Conference
• /
• 1997.11a
• /
• pp.151-156
• /
• 1997

본 논문은 저비용이면서 정확한 제어를 수행하는 새로운 퍼지 제어기의 VHDL 설계 및 FPGA 구현을 자동적으로 수행하는 통합 개발 환경(IDE : Integrated Development Environment)을 다룬다. 이를 위해 FLC의 자동 설계 및 구현의 전 과정을 하나의 환경 내에서 개발 가능하게 하는 퍼지 제어기 자동 설계 및 구현 시스템 (FLC Automatic Design and Implementation Station :FADIS)을 개발하였는데 이 시스템은 다음 기능을 포함한다. (1) 원하는 퍼지 제어기의 설계 파라메터를 입력받아 이로부터 FLC를 구성하는 각 모듈의 VHDL 코드를 자동적으로 생성한다. (2) 생성된 각 모듈의 VHDL 코드가 원하는 동작을 수행하는지를 Synopsys사의 VHDL Simulator상에서 시뮬레이션을 수행한다. (3) Synopsys사의 FPGA Compiler에 의해 VHDL 코드를 합성하여 FLC의 각 구성 모듈을 얻는다. (4) 합성된 모듈은 Xilinx사의 XactSTep 6.0에 의해 최적화 및 배치, 배선이 이루어진다. (5) 얻어진 Xilinx rawbit 파일은 VCC사의 r2h에 의해 C 언어의 header 파일 형태의 하드웨어 object로 변환된다. (6) 하드웨어 object를 포함하는 응용 제어 프로그램의 실행 파일을 재구성 \ulcorner 능한 FPGA 시스템 상에 다운로드한다. (7) 구현된 FLC의 동작 과정은 구현된 FLC와 제어 target 사이의 상호 통신에 의해 모니터링한다. 트럭 후진 주차 제어에 사용하는 퍼지 제어기 설계 및 구현의 전 과정을 FADIS상에서 수행하여 FADIS가 완전하게 동작하는지를 확인하였다.

• The Transactions of the Korea Information Processing Society
• /
• v.7 no.10
• /
• pp.3247-3261
• /
• 2000

In recent years, as the complexity of signal processmg systems Increases, the needs for dcslgners to mlx up hardware-part and software-part grow more and more considering both performance and cost There exist many algorilhms In C for vanous Signal processung apphcations. We have to translate the algonlhm C to hardware descnptlon language(HDL), If portion or the algonlhm needs to be unplcmenled in hardwarc pari of the syslcm. For this translation. it's dtfftcult to handle dynamic memory allocalion, function calls, pointer manipoJalion. This research shows a design method for a hardware model about recursive calls which was classified into software part of the system previously [or the translation from C to VHDL. The benefits of havlIlg recursive calls m hardware structure can be quite high since provides flexbility in hardware/software partitioming in codesign sysem.

• The Journal of the Institute of Internet, Broadcasting and Communication
• /
• v.21 no.1
• /
• pp.99-105
• /
• 2021

Today, a superscalar processor is the basic unit or an essential component of a multi-core processor, SoCs, and GPUs. Hence, a high-performance out-of-order superscalar processor must be adopted for these systems to maximize its performance. The superscalar processor fetches, issues, executes, and writes back multiple instructions per cycle by utilizing reorder buffers and reservation stations to dynamically schedule instructions in a pipelined scheme. In this paper, a fully pipelined out-of-order superscalar processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, the program composed of ARM instructions is successfully performed.

• Proceedings of the IEEK Conference
• /
• 2000.06d
• /
• pp.178-181
• /
• 2000

In this paper, we present the implementation of filterbank for MPEG-2 Advanced Audio Coding (AAC) decoder with VHDL. The filterbank of AAC employs a technique called time-domain aliasing cancellation (TDAC). In order to make the algorithm more efficiently, we decompose and reorganize the filterbank algorithm lot the high speed decoding process and lower computational cost. And we make this filterbank algorithm to be used with other modules of AAC decoder in parallel processing.

• Proceedings of the IEEK Conference
• /
• 2000.11d
• /
• pp.183-186
• /
• 2000

Motion estimation technique has been used to increase video compression rates in motion video applications. One of the important algorithms to implement the motion estimation technique is search algorithm. Among many search algorithms, the H.263 adopted the Nearest Neighbors algorithm for fast search. In this paper, motion estimation block for the Nearest Neighbors algorithm is designed on FPGA and coded using VHDL and simulated under the Xilinx foundation environments. In the experiment results, we verified that the algorithm was properly designed and performed on the Xilinx FPGA(XCV300Q240)

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.1065-1068
• /
• 1998

This paper proposes a new test generation method. Most of the test generation methods are gate-level based, but our scheme is VHDL based, especially in other word, behavioral-level based. Our test pattern generation method uses software test method. And we generate deterministic test pattern with this method. The purpose of our method is to reduce the time and effort to generate the test patterns for the end-product test of IC.