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http://dx.doi.org/10.7236/JIIBC.2021.21.1.99

VHDL Design for Out-of-Order Superscalar Processor of A Fully Pipelined Scheme  

Lee, Jongbok (School of ME Engineering, Hansung University)
Publication Information
The Journal of the Institute of Internet, Broadcasting and Communication / v.21, no.1, 2021 , pp. 99-105 More about this Journal
Abstract
Today, a superscalar processor is the basic unit or an essential component of a multi-core processor, SoCs, and GPUs. Hence, a high-performance out-of-order superscalar processor must be adopted for these systems to maximize its performance. The superscalar processor fetches, issues, executes, and writes back multiple instructions per cycle by utilizing reorder buffers and reservation stations to dynamically schedule instructions in a pipelined scheme. In this paper, a fully pipelined out-of-order superscalar processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, the program composed of ARM instructions is successfully performed.
Keywords
fully pipelined; out-of-order; superscalar; VHDL;
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