소프트웨어 검사방법을 이용한 VHDL 설계에서의 테스트 패턴 생성

Test Pattern Generation in VHDL Design using Software Testing Method

This paper proposes a new test generation method. Most of the test generation methods are gate-level based, but our scheme is VHDL based, especially in other word, behavioral-level based. Our test pattern generation method uses software test method. And we generate deterministic test pattern with this method. The purpose of our method is to reduce the time and effort to generate the test patterns for the end-product test of IC.