• 한국통신학회:학술대회논문집
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• 한국통신학회 2006년도 하계종합학술발표회 논문 초록집
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• pp.219-219
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• 2006

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.49-52
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• 1999

In this paper, we describe the structure of the DWMT (discrete wavelet multitone) transceiver for VDSL system. The DWMT transceiver is basically consisted of the transmultiplexer using cosine modulation filter bank (CMFB), time domain equalizer (TEQ) and frequency domain equalizer (FEQ) minimizing the effects of the transmission channel. For FEQ, we expanded the general LMS algorithm to 2-dimensions: time and subchannel axes and examined the 2-dimensional LMS methods with the various array size.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.81-85
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• 1999

DWMT VDSL system needs A/D converter clock, bit clock, symbol clock, frame clock, etc. DMT ADSL system utilizes a correlation method which makes use of cyclic prefix or preamble pattern for clock recovery. But the correlation method is difficult to apply to the DWMT system because modulated symbols are overlapped in the time domain. This paper proposes a novel clock recovery method which can be used for the DWMT system due to its inherent independence of the modulation method. This new method is verified by SPICE simulations.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(1)
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• pp.315-318
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• 2002

In this paper, we studied a now VDSL frequency plan mode 6 for improved\ulcorner symmetric 10MDSL service. The frequency plan 998 for asymmetric and frequency plan 997 for symmetric have arc not optimally designed for 10MDSL service. To improve reach and rates of 10MDSL, we proposed for a now frequency plan. According to the results of our simulation studios of newly Proposed mode 6 frequency plan which compared to plan 998, 997, and ethers[2], the new scheme gives an improved performance in rates and reach.

• 산업기술연구
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• 제22권B호
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• pp.169-173
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• 2002

In this paper, we discussed an effective VDSL frequency plan for symmetric 10MDSL service. The frequency plan 998 and plan 997 for asymmetric VDSL services have been not optimally designed for 10MDSL services. To obtain the reaches and data rates of 10MDSL, we proposed two frequency allocation schemes : Static method and dynamic method. We can select frequency bands with their fixed boundaries in static method while with their variable boundaries in dynamic method. To show the effectiveness of our proposed methods, we performed some simulations about plan 997 and plan 998, new static method, and new dynamic method. According to the simulation results, the proposed dynamic method can provide the best data rates and reaches for 10 Mbps symmetric VDSL services.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
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• pp.289-293
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• 2004

In this paper, data rate of VDSL system was analyzed in RFI(Radio Frequency Interference) environment. This Paper used Various 'VDSL Test Loop' suggested by ANSI DSL Standard group TIE1.4.Many parameters, 'Noise Model A', 'Noise Model F' and KARL-HAM band are used for more accurate results of the simulation. Most of conditions for simulation are followed to the ANSI Standard 'Spectrum management'. Many results have been calculated according to the different conditions of the test loops in simulation. Simulation results confirm that using shaped PSD mask to reject RFI is one of factor to decrease the performance of VDSL systems.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 통신소사이어티 추계학술대회논문집
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• pp.7-10
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• 2003

VDSL(Very-high-rate Digital subscriber Line) have a severe FEXT(Far-End Crosstalk). This paper proposes FEXT cancelation scheme in VDSL system. The scheme is GDFE(Generalize Decision Feedback Equalizer) and Vectored-DMT (Discrete Multitone). Feedback part of GDFE decreases FEXT noise. Canceler and Precoder block a part of Vectored-DMT eliminate FEXT. After all, simulation result show improvement of transmit and receive speed.

• JSTS:Journal of Semiconductor Technology and Science
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• 제10권4호
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• pp.282-291
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• 2010

This paper presents a full-CMOS transmitter and receiver for VDSL2 systems. The transmitter part consists of the low-pass filter, programmable gain amplifier (PGA) and 14-bit DAC. The receiver part consists of the low-pass filter, variable gain amplifier (VGA), and 13-bit ADC. The low pass filter and PGA are designed to support the variable data rate. The RC bank sharing architecture for the low pass filter has reduced the chip size significantly. And, the 80 Msps, high resolution DAC and ADC are integrated to guarantee the SNR. Also, the transmitter and receiver are designed to have a wide dynamic range and gain control range because the signal from the VDSL2 line is variable depending on the distance. The chip is implemented in 0.25 ${\mu}m$ CMOS technology and the die area is 5 mm $\times$ 5 mm. The spurious free dynamic range (SFDR) and SNR of the transmitter and receiver are 67.5 dB and 41 dB, respectively. The power consumption of the transmitter and receiver are 160 mW and 250 mW from the supply voltage of 2.5 V, respectively.

• 전자공학회논문지SC
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• 제37권2호
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• pp.77-84
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• 2000

본 논문에서는 51.84Mbps의 전송 속도를 갖고, 16-QAM 변조방식을 사용하는 VDSL(고속 디지털 가입자 루프) 시스템에서, 전송 신호 주파수 스펙트럼의 밴드-에지 성분을 최대화함으로써 심볼 클록(12.96㎒)을 복원하는 방식에 대해 논의한다〔1〕. 디지털 방식의 PLL에서 여러 가지 특성들이 조사되었으며, NCO(Numerically Controlled Oscillator)에서 사용하는 룩-업 테이블의 효율적인 설계 방식을 제시하였다.

• 한국통신학회논문지
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• 제27권10C호
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• pp.951-962
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• 2002

DMT 방식의 송·수신기는 파일롯 채널의 페이즈 정보를 이용하여 샘플동기를 맞추게 된다. 파일롯 채널의 페이즈 값은 심볼 단위로 행해지는 FFT 결과에서 구할 수 있으므로, 심볼동기를 샘플동기 이전에 맞추어 주어야 한다. DMT VDSL시스템의 경우, 심볼 내의 반복되는 구간사이의 상관성을 통해서 심볼동기를 구할 수 있게 된다. 수신신호의 부호를 기본으로한 최우도 추정함수를 사용하여 심볼동기를 구하는 기법에 대해 제안하였으며, Tx 윈도우에 의해, 심볼동기의 추정값이 잡음에 민감해지는 것을 막기위해 가중합을 적용한 추정 방법을 제안하였다. 송·수신기 사이에 샘플링 클럭 옵셋이 존재할 경우, 샘플동기를 위해 디지털 영역에서 샘플링 클럭 옵셋을 보정해주는 기법을 제안하였다.