• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.47-54
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• 2004

The growth of computer resource and network speed has increased requests for the use of remotely located computer systems by connecting through computer networks. This phenomenon has hoisted research activities for application service provision that uses server-based remote computing paradigm. The server-based remote computing paradigm has been developed as the ASP (Application Service Provision) model, which provides remote users through application sharing protocol to application programs. Security requirement such as confidentiality, availability, integrity should be satisfied to provide ASP service using centralized computing system. Existing Telnet or FTP service for a remote computing systems have satisfied security requirement by a simple access control to files and/or data. But windows-based centralized computing system is vulnerable to confidentiality, availability, integrity where many users use the same application program installed in the same computer. In other words, the computing system needs detailed security level for each user different from others, such that only authorized user or group of users can run some specific functional commands for the program. In this paper, we propose windows based centralized computing system that sets security policies for each user for the use of instructions of the application programs, and performs access control to the instructions based on the security policies. The system monitors all user messages which are executed through graphical user interface by the users connecting to the system. Ail Instructions, i.e. messages, for the application program are now passed to authorization process that decides if an Instruction is delivered to the application program based on the pre-defined security polices. This system can be used as security clearance for each user for the shared computing resource as well as shared application programs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.6
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• pp.59-70
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• 2004

SMT(Simultaneous Multi Threading) architecture uses TLP(Thread Level Parallelism) and increases processor throughput, such that issue slots can be filled with instructions from multiple independent threads. Having multiple ready threads reduces the probability that a functional unit is left idle, which increases processor efficiency. To utilize those advantages for the SMT processors, the issue unit must control the flow of instructions from different threads and not create conflicts among those instructions, which make the SMT issue logic extremely complex. Therefore, our SMT architecture, which is modeled in this paper, uses an in-order-issue and completion scheme, and therefore, can use a simple issue mechanism with a scoreboard already instead of using register renaming or a reorder buffer. However, an SMT scoreboarding mechanism is still more complex and costlier than that of a single threaded conventional processor. This paper proposes an optimal implementation of a scoreboarding mechanism for an ARM-based SMT architecture.

• Journal of Korean Elementary Science Education
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• v.18 no.2
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• pp.79-101
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• 1999

Astronomy is a good area to introduce a student to the study of science. The student often questions what causes the change in seasons, in the day and right, and in the rotation of stars, etc. Attempts to find answers to problems related to these astronomical observations influence the student`s intellectual development. This study is to investigate the effect of running an astronomical observations program on the preservice elementary teachers' astronomy achievement, astronomy teaching efficacy beliefs, and scientific attitude. Students consist of twenty four preservice elementary teachers. Three instruments are used: one is the astronomy achievement test, which is of an essay type, and 5 items. The other is the astronomy teaching efficacy beliefs test, which is of a Likert scale type, and 22 items. Another is the scientific attitude test, which is of the Likert scale type, and 10 items. Data are collected before and after instruction in the astronomical observations program, through the use of these tests. Data are compared. The results are: \circled1There is a significant difference between before and after instructions in the astronomy achievement test(t=11.31, p=000). \circled2There is a significant difference between before and after instructions in the astronomy teaching efficacy beliefs test(t=5.98, p=.000). \circled3There is a significant difference between before and after instructions in the scientific attitude test(t=270, pde. There fore, the a=.013). As a result, running an astronomical observations program has an effect on the preservice elementary teachers' astrono my achievement, astronomy teaching efficacy beliefs, and scientific attituuthor urges the teacher to teach astronomy through the astronomical observations in school.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.5
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• pp.143-149
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• 2020

Currently, a multi-core processor is mainly used as a central processing unit of a computer system, and a high-performance out-of-order processor is adopted as each core to maximize system performance. The early out-of-order execution processor with Tomasulo algorithm aimed at floating-point instructions, and it took several cycles to execute by the use of complex structures such as reorder buffer and reservation station. However, in order for the processor to properly utilize out-of-order execution and increase the throughput of instructions, it must operate in a fully pipelined manner. In this paper, a fully pipelined out-of-order processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, a program composed of ARM instructions is successfully performed.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.285-288
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• 2008

Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1221-1230
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• 1990

This paper presents a code generation method and an effective handling algorithm of ingeger constant multiplication for RISC machines in compiler design. As RISC Architectures usually use faster and more simply formed instructions than CISC's and most RISC processors do not have an integer multiplication instruction, it is required an effective algorithm to process integer multiplication. For the proposed code generator, Portable C Compiler(PCC) is redesigned to be suitable for an RISC machine, and composed an addition chain is built up to allow fast execution of constant multiplication, a part of integer one whicch appears very frequency in code generation phase.

• Proceedings of the Korean Society of Marine Engineers Conference
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• 2005.11a
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• pp.204-205
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• 2005

The following instructions give you basic guidelines for preparing camera-ready papers for the proceeding of the KOSME. We recommend you to use the HWP word processor.

• The Journal of the Korean dental association
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• v.20 no.3 s.154
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• pp.233-237
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• 1982

A review of the literature was presented, illustrating the effect that gingivally retained orthodontic elastic bands have on the periodontal tissues. A case report was presented for treatment of mobile maxillary central incisors secondary to a subgingival elastic band. Following surgical removal of elastic band and periodontal debridement, the teeth were successfully retained with active orthodontic appliances. Until a harmless radiopaque medium can be safely incorporated into elastic bands, extreme caution in their use should be observed. Not only should all attempts be made to anchor the elastic bands to the clinical crown, but the patient should receive through instructions in their placement and removal.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.2
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• pp.200-208
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• 2000

Multi-ports register could shared several instructions at the same time in read operation. We address a formal methods for describing timing analysis and resource restriction in pipeline super scalar process that having multi-Port registers. First, we specify in-order pipeline instructions, and then, extend timing analysis in out-of-order super-scalar. In this case, we find instruction pairs in any cycle which can execute same time, We use ACSR(Algebra of Communicating Shared Resources), a branch of formal methods based on process algebra, for instruction specification and modelling.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.9
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• pp.33-40
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• 2008

As the speed of memory is improved vey fast the advanced test equipments are needed to test the ultra-high speed memory devices efficiently. It is necessary to develop the Algorithmic Pattern Generator (ALPG) that tests fast memory devices effectively using the instructions that testers want to use. In this paper, we propose a new parallel ALPG for the ultra-high speed memory testing. The proposed ALPG can generate patterns for fast memory devices at high speed using manual instructions by the Instruction Analyzer.