[KSCI] Korea Science Citation Index Service

A Design of a 8-Thread Graphics Processor Unit with Variable-Length Instructions

Lee, Kwang-Yeob (Dept. of Computer Engineering, Seokyeong University)
Kwak, Jae-Chang (Dept. of Computer Science, Seokyeong University)

Publication Information

Journal of information and communication convergence engineering / v.6, no.3, 2008 , pp. 285-288 More about this Journal

Abstract

Most of multimedia processors for 2D/3D graphics acceleration use a lot of integer/floating point arithmetic units. We present a new architecture with an efficient ALU, built in a smaller chip size. It reduces instruction cycles significantly based on a foundation of multi-thread operation, variable length instruction words, dual phase operation, and phase instruction's coordination. We can decrease the number of instruction cycles up to 50%, and can achieve twice better performance.

Keywords

3D Graphics Accelerator; OpenGL ES 2.0; Shader; Multi-thread; Variable Length Instruction;

Citations & Related Records

Reference

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2	H.K. Jeong, 'Design of 3D Graphics Geometry Accelerator using the Programmable Vertex Shader' ITC-CSCC 2006
3	Liza Fireman, 'The Complexity of SIMD Alignment' Technion - Computer Science Department - M.Sc. Thesis MSC - 2006
4	James C. Lelterman, 'Learn Vertex and Pixel Shader Programming with DirectX9' Wordware Publishing, Inc. 2004