• Title/Summary/Keyword: Upper gate

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A Study on the Academic Discussion on the Presence of Upper and Lower Gates of Urinary Bladder (방광(膀胱)의 상하구(上下口) 유무(有無) 논쟁에 대한 고찰(考察))

  • Baik, Yousang;Jung, Hyuksang;Kim, Dohoon
    • Journal of Korean Medical classics
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    • v.30 no.2
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    • pp.83-98
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    • 2017
  • Objectives : The paper's objective is to study into the books dealing in the debate surrounding the existence, or nonexistence, of urinary bladder's upper gate and lower gate, a debate that ensured since the publication of Huangdineijing. Methods : Sikuquanshu and Zhongyishijia databases were searched to collect related materials, and these materials were reviewed to get an understanding of the historical development of the debate. Results : The upper gates of urinary bladder was first mentioned in Nanjing. Since then, Wanglu's Yijingsuhuiji asserted that the upper gate exists while the lower didn't, but many argued after the dawning of Ming Dynasty that the upper doesn't exist while the lower does. Additionally, some urged in relation to the assertion of the nonexistence of upper gate that water liquid pervades into the urinary bladder through sebaceous membrane or oil net. Conclusions : Behind the debate between the existence or nonexistence of the upper and lower gates in urinary bladder is the theory of qi transformation. Even the anatomical knowledge of urinary bladder was submitted as an evidence. In general, the debate developed depending on how the differences between Huangdineijing's osmotic opinion and Nanjing's existence of the upper gate were perceived.

A Study on the Cause and the Effect of the Widths of Sung-Rye-Mun Gate Arches (숭례문 홍예너비와 도로 폭 및 문루 어간(御間)거리의 상관성 연구 - 화성(華城) 팔달문(八達門), 흥인지문(興仁之門)과 비교를 통하여 -)

  • Ryoo, Seong-Lyong
    • Journal of architectural history
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    • v.19 no.2
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    • pp.117-132
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    • 2010
  • The Great south gate of Seoul Castle, Sung-Rye-Mun, the east gate of Seoul Castle, Hung-In-Ji-Mun, the south gate of Hwa-Sung Castle, Pal-Dal-Mun and the north gate of Hwa-Sung Castle, Jang-An-Mun are typical significant castle gate of Chosun Dynasty. They have a lot in common with exterior. Additionally there are also something common in dimensions. At first, the arch dimensions of lower story is very similar and the columns of upper story are the regular intervals. Purpose of this study is to confirm similarities above mentioned were intended on purpose and if then what was the reason. The results of this study were described separately as follows. 1. The widths of the arches were based on each 16Cheok and 18Cheok. 2. The heights of the arches followed less strictly rule than the widths. 3. The widths of the arches, 16Cheok was same size as width of middle-size road (中路, Jung-Ro) inside the Castle town in Chosun Dynasty. 4. The widths of the arches, 16Cheok was the standard size of exit went through castle and then the standard size of road arrived at one's destination. 5. The widths of the arches had an effect on the intervals between the columns of the upper story. Finally we recognized that in Chos${\u{o}}$n Dynasty the widths of the gate arches in Seoul castle and Hwa-Sung castle had relevance to the city planning largely and widths of the gate arches had an effect on the intervals between the columns of the upper story partly.

Effects of $WSi_x$, thickness and F concentration on gate oxide characteristics in tungsten polycide gate structure (Tungsten polycide gate 구조에서 $WSi_x$ 두께와 fluorine 농도가 gate oxide 특성에 미치는 영향)

  • 김종철
    • Journal of the Korean Vacuum Society
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    • v.5 no.4
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    • pp.327-332
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    • 1996
  • In this study, the effects of $WSi_x$, thickness and fluorine concentration in tungsten polycide gate structure on gate oxide were investigated. As $WSi_x$, thickness increases, gate oxide thickness increases with fluorine incorporation in gate oxide, and time-to-breakdown($T_{BD,50%}$) of oxide decreases. The stress change with $WSi_x$ thickness was also examined. But it is understood that the dominant factor to degrade gate oxide properties is not the stress but the fluorine, incorporated during $WSi_x$ deposition, diffused into $WSiO_2$ after heat treatment. In order to understand the effect of fluorine diffusion into oxidem fluorine ion implanted gates were compared. The thickness variation and $T_{BD,50%}$ of gate oxide is saturated over 600 $\AA$ thickness of $WSi_x$. The TEM and SIMS studies show the microstructure less than 600 $\AA$ thickness is dense and flat in surface. However, over 600$\AA$, the microstructure of $WSi_x$ is divided into two parts: upper porous phase with rugged surface and lower dense phase with smmoth interface. And this upper phase is transformed into oxygen rich crystalline phase after annealing, and the fluorine is captured in this layer. Therefore, the fluorine diffusion into the gate oxide is saturated.

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A Study on Improvement of a-Si:H TFT Operating Speed

  • Hur, Chang-Wu
    • Journal of information and communication convergence engineering
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    • v.5 no.1
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    • pp.42-44
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    • 2007
  • The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of $8{\mu}m{\sim}16{\mu}m$ and width of $80{\sim}200{\mu}m$ after depositing with gate electrode (Cr) $1500{\AA}$ under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these, thin films is formed with a-SiN:H ($2000{\mu}m$), a-Si:H($2000{\mu}m$) and $n^+a-Si:H$ ($500{\mu}m$). We have deposited $n^+a-Si:H$, NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the $n^+a-Si:H$ layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain show drain current of $8{\mu}A$ at 20 gate voltages, $I_{on}/I_{off}$ ratio of ${\sim}10^8$ and $V_{th}$ of 4 volts.

A Study on Decision of gate location for Injection molding of Automobile air cleaner Upper cover (자동차용 에어클리너 상부커버 사출성형에서 게이트의 위치 결정)

  • Jang, Sung-Min;Kim, In-Soo
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.16 no.7
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    • pp.4411-4417
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    • 2015
  • The proper design of the gate location for injection molding of plastic goods is obtained from three-dimensional injection molding analysis for various design alternatives. This paper is study on effect of gate location in injection molding. It have a decisive impact on productivity and quality of plastic goods. This objectives of this paper is to analysis effect of hot runner gate location for resin filling, weld line, injection pressure to manufacture of automobile air cleaner upper case with injection molding machine. Thus, to analysis these problems in this paper, location of gate are gave variety in 4 CASEs. In this paper, the CAE simulation considering each variations in location of gate is performed to predict the cause of faulty which appears in the injection molding process.

Metal Insulator Gate Geometric HEMT: Novel Attributes and Design Consideration for High Speed Analog Applications

  • Gupta, Ritesh;Kaur, Ravneet;Aggarwal, Sandeep Kr;Gupta, Mridula;Gupta, R.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.10 no.1
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    • pp.66-77
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    • 2010
  • Improvement in breakdown voltage ($BV_{ds}$) and speed of the device are the key issues among the researchers for enhancing the performance of HEMT. Increased speed of the device aspires for shortened gate length ($L_g$), but due to lithographic limitation, shortening $L_g$ below sub-micrometer requires the inclusion of various metal-insulator geometries like T-gate onto the conventional architecture. It has been observed that the speed of the device can be enhanced by minimizing the effect of upper gate electrode on device characteristics, whereas increase in the $BV_{ds}$ of the device can be achieved by considering the finite effect of the upper gate electrode. Further, improvement in $BV_{ds}$ can be obtained by applying field plates, especially at the drain side. The important parameters affecting $BV_{ds}$ and cut-off frequency ($f_T$) of the device are the length, thickness, position and shape of metal-insulator geometry. In this context, intensive simulation work with analytical analysis has been carried out to study the effect of variation in length, thickness and position of the insulator under the gate for various metal-insulator gate geometries like T-gate, $\Gamma$-gate, Step-gate etc., to anticipate superior device performance in conventional HEMT structure.

The Development of Small Sluice gate systems without Upper Concrete structure (상부 콘크리트 구조물이 없는 소형 수문 시스템 개발)

  • Kook, Jeong-Han;Kim, Key-Sun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.11
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    • pp.4738-4744
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    • 2011
  • This study proposes the system of new small sluice gate operated without the upper concrete structure. The new mechanism is composed of hydraulic system, driving mechanism to feed the floodgate up and down, hydrological locking device, safety device and etc. The hydraulic pumps and control systems away from the location of the sluice gate systems are installed and controled in place. The feed device with the hydraulic rack, pinion and hydraulic actuator is installed on the side of the sluice gate. The following results take the advantages of cost reduction, operation safety and compact product.

Gate Drive Circuit of a Classic Converter for a Switched Reluctance Motor (Switched Reluctance Motor용 Classic Converter의 Gate 구동회로)

  • Lim, J.Y.;Cho, K.Y;Shin, D.J.;Kim, C.H.;Kim, J.C.
    • Proceedings of the KIEE Conference
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    • 1995.07a
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    • pp.325-327
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    • 1995
  • A new gate drive circuit of classic converter for a switched reluctance motor is presented. Conventional gate drive circuit usually consists of the isolated power supplies and signal transferring devices for isolation, such as photo coupler, pulse transformer, and gate drive chips. The proposed gate drive circuit consists of resistors, capacitors, and zenor diodes without isolated power supplies, that make the drive circuit simple and reduce the material cost. The operational modes are classified and analyzed. The characteristics of the phase current and the gate signal of upper switches is investigated with the variation of duty ratio through the experiments.

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The Fabrication of a-Si:H TFT Improving Parasitic Capacitance of Source-Drain (소오스-드레인 기생용량을 개선한 박막트랜지스터 제조공정)

  • 허창우
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.8 no.4
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    • pp.821-825
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    • 2004
  • The a-Si:H TFTs decreasing parasitic capacitance of source-drain is fabricated on glass. The structure of a-Si:H TFTs is inverted staggered. The gate electrode is formed by patterning with length of 8 ${\mu}m∼16 ${\mu}m. and width of 80∼200 ${\mu}m after depositing with gate electrode (Cr) 1500 under coming 7059 glass substrate. We have fabricated a-SiN:H, conductor, etch-stopper and photoresistor on gate electrode in sequence, respectively. The thickness of these thin films is formed with a-SiN:H (2000 ), a-Si:H(2000 ) and n+a-Si:H (500). We have deposited n+a-Si:H ,NPR(Negative Photo Resister) layer after forming pattern of Cr gate electrode by etch-stopper pattern. The NPR layer by inverting pattern of upper gate electrode is patterned and the n+a-Si:H layer is etched by the NPR pattern. The NPR layer is removed. After Cr layer is deposited and patterned, the source-drain electrode is formed. The a-Si:H TFTs decreasing parasitic capacitance of source-drain has channel length of 8 ~20 ${\mu}m and channel width of 80∼200 ${\mu}m. And it shows drain current of 8 ${\mu}A at 20 gate voltages, Ion/Ioff ratio of 108 and Vth of 4 volts.

Dual Gate-Controlled SOI Single Electron Transistor: Fabrication and Coulomb-Blockade

  • Lee, Byung T.;Park, Jung B.
    • Journal of Electrical Engineering and information Science
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    • v.2 no.6
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    • pp.208-211
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    • 1997
  • We have fabricated a single-electron-tunneling(SET) transistor with a dual gate geometry based on the SOI structure prepared by SIMOX wafers. The split-gate is the lower-gate is the lower-level gate and located ∼ 100${\AA}$ right above the inversion layer 2DEG active channel, which yields strong carrier confinement with fully controllable tunneling potential barrier. The transistor is operating at low temperatures and exhibits the single electron tunneling behavior through nano-size quantum dot. The Coulomb-Blockade oscillation is demonstrated at 15mK and its periodicity of 16.4mV in the upper-gate voltage corresponds to the formation of quantum dots with a capacity of 9.7aF. For non-linear transport regime, Coulomb-staircases are clearly observed up to four current steps in the range of 100mV drain-source bias. The I-V characteristics near the zero-bias displays typical Coulomb-gap due to one-electron charging effect.

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