• ETRI Journal
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• 제27권5호
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• pp.569-578
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• 2005

The purpose of this paper is to describe the implementation of monolithically matching circuits, interface circuits, and RF core circuits to the same substrate. We designed and fabricated on-chip 1 to 6 GHz up-conversion and 1 to 8 GHz down-conversion mixers using a 0.8 mm SiGe hetero-junction bipolar transistor (HBT) process technology. To fabricate a SiGe HBT, we used a reduced pressure chemical vapor deposition (RPCVD) system to grow a base epitaxial layer, and we adopted local oxidation of silicon (LOCOS) isolation to separate the device terminals. An up-conversion mixer was implemented on-chip using an intermediate frequency (IF) matching circuit, local oscillator (LO)/radio frequency (RF) wideband matching circuits, LO/IF input balun circuits, and an RF output balun circuit. The measured results of the fabricated up-conversion mixer show a positive power conversion gain from 1 to 6 GHz and a bandwidth of about 4.5 GHz. Also, the down-conversion mixer was implemented on-chip using LO/RF wideband matching circuits, LO/RF input balun circuits, and an IF output balun circuit. The measured results of the fabricated down-conversion mixer show a positive power conversion gain from 1 to 8 GHz and a bandwidth of about 4.5 GHz.

• 대한전자공학회논문지TC
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• 제41권12호
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• pp.103-108
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• 2004

본 논문에서는 낮은 LO 입력으로 저 변환손실 특성을 갖는 MIMIC(Millimeter-wave Monolithic Integrated Circuit) V-band up-mixer를 설계 및 제작하였다. Up-mixer는 0.1 ㎛ GaAs PHEMT와 coplanar waveguide (CPW) 전송라인을 사용하여 제작되었다. Up-mixer는 60.4 GHz의 RF 주파수, 2.4 GHz의 IF 주파수와 58 GHz의 LO 주파수에서 동작되도록 설계되었다. Up-mixer는 표준 MIMIC공정을 사용하여 제작되었으며 칩 크기는 2.3 mmxl.6 mm이다. 제작된 up-mixer의 측정결과 입력신호가 -10.25 dBm 이고 LO의 입력 전력이 5.4 dBm 일 때 1.25 dB의 양호한 변환손실 특성을 얻었다. 58 GHz에서 LO 와 RF의 격리특성은 -13.2 dB를 나타내었다. 제작된 V-band up-mixer는 기존에 발표된 밀리미터파 up-mixer에 비하여 낮은 LO 입력 전력과 양호한 변환손실 특성을 나타내었다.

• Journal of electromagnetic engineering and science
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• 제8권3호
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• pp.91-95
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• 2008

This paper presents a direct-conversion I/Q up-mixer block, which supports $3{\sim}5$ GHz ultra-wideband(UWB) applications. It consists of a VI converter, a double-balanced mixer, a RF amplifier, and a differential-to-single signal converter. To achieve wideband characteristics over $3{\sim}5$ GHz frequency range, the double-balanced mixer adopts a shunt-peaking load. The proposed RF amplifier can suppress unwanted common-mode input signals with high linearity. The proposed direct-conversion I/Q up-mixer block is implemented using $0.18-{\mu}m$ CMOS technology. The measured results for three channels show a power gain of $-2{\sim}-9$ dB with a gain flatness of 1dB, a maximum output power level of $-7{\sim}-14.5$ dBm, and a output return loss of more than - 8.8 dB. The current consumption of the fabricated chip is 25.2 mA from a 1.8 V power supply.

• KIEE International Transactions on Electrophysics and Applications
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• 제4C권6호
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• pp.272-275
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• 2004

A balanced single side-band (SSB) mixer employing a sub-harmonic configuration is designed for up and down conversions in K-band. The designed mixer uses anti-parallel diode (APD) pairs to effectively eliminate even harmonics of the local oscillator (LO) spurious signal. To reduce the odd harmonics of LO at the RF port, we employ a balanced configuration for LO. The fabricated chip shows 12$\pm$2dB of conversion loss and image-rejection ratio of about 20dB for down conversion at RF frequencies of 24-27.5GHz. As an up-conversion mode, the designed chip shows 12dB of conversion loss and image-rejection ratio of 20 ～ 25 dB at RF frequencies of 25 to 27GHz. The odd harmonics of the LO are measured below -37dBc.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 하계종합학술대회 논문집(5)
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• pp.61-64
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• 2000

This paper describes a RF Down-Conversion Mixer for mobile communication systems. This circuit achieves low voltage operation and low power consumption by reducing stacked devices of conventional gilbert cell mixer. In order to reduce stacked devices, we use source-follower structure. The proposed RF Down-Conversion mixer operates up to 1.85GHz at 1.5V power supply with 0.25um CMOS technology and consumes 2.2mA.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권1호
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• pp.30-40
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• 2002

A 2.45GHz double-balanced modified Gilbert-type CMOS up-conversion mixer design is introduced, where the PMOS current-reuse bleeding technique is demonstrated to be efficient in improving conversion gain, linearity, and noise performance. An LO buffer is included in the mixer design to perform single-ended to differential conversion of the LO signal on chip. Simulation results of the design based on careful modeling of all active and passive components are examined to explain in detail about the characteristic improvement and degradation provided by the proposed design. Two kinds of chips were fabricated using a standard $0.35\mu\textrm$ CMOS process, one of which is the mixer chip without the LO buffer and the other is the one with it. The measured characteristics of the fabricated chips are quite excellent in terms of conversion gain, linearity, and noise, and they are in close match to the simulation results, which demonstrates the adequacy of the modeling approach based on the macro models for all the active and passive devices used in the design. Above all the benefits provided by the current-reuse bleeding technique, the improvement in noise performance seems most valuable.

• 전기전자학회논문지
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• 제4권2호
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• pp.202-211
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• 2000

회로 시뮬레이터인 SPICE를 이용하여 1.9GHz 대역의 CMOS up-conversion 믹서를 설계하였고, 회로 설계를 위한 시뮬레이션 과정을 소자 모델링을 포함하여 상세히 설명하였다. $0.5{\mu}m$ 표준 CMOS 공정을 이용하여 칩을 제작한 결과, 제작된 칩의 특성과 초기 시뮬레이션에 의해 예상되는 특성 사이에 큰 차이점이 발견되어 이에 대한 원인 분석을 시도하였다. 발견된 문제점들을 고려한 경우의 시뮬레이션을 통해 시도한 시뮬레이션 방법의 타당성을 증명하였고, 이러한 문제점들을 보완할 경우 사용한 표준 CMOS 공정으로도 GaAs MESFET 공정을 사용한 유사 칩의 특성에 근접하는 칩 특성의 구현이 가능함을 보였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.113-114
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• 2006

In this paper, dual-gate mixer has been designed and optimized to have variable conversion gain for WiBro and WLAN applications and to save power. With the LO power of 0dBm and RF power of -50dBm, the mixer shows 15dB conversion gain. When RF power increases from -50dBm to -20dBm, the conversion gain decreases to -2dB with bias change. The variable conversion gain can reduce the high dynamic range requirement of AGC burden at IF stage. Also, it can save the dc power dissipation of mixer up to 90%.

• 한국전자파학회논문지
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• 제27권9호
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• pp.825-833
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• 2016

본 논문에서는 $0.18{\mu}m$ CMOS 공정을 사용한 저 전력 고 이득 주파수 상향변환기를 이용하여 IEEE 802.15.4 규격을 만족하는 직접 변환 송신기를 제안 및 설계한다. 설계된 RF 직접 변환 송신기는 차동입력 디지털-아날로그 변환기, 수동 저역통과 필터, 가변이득 증폭기, Quadrature 주파수 상향 변환기 그리고 차동 출력 구동증폭기로 구성되어 있다. 제안하는 직접변환 송신기에서 핵심적인 부분은 2.4 GHz Zigbee 규격을 저 전력으로 구동하는데 있다. 특히 Quadrature 주파수 상향변환기는 이득 Boosting을 통하여 적은 전류 소모로도 충분한 이득과 선형성을 보이고 있다. 측정결과, 공급전압 1.2 V에서 송신기의 총 소모 전류는 7.8 mA이고, 최대 출력 전력은 0 dBm 이상 그리고 -30 dBc의 ACPR(Adjacent Channel Power Ratio)을 나타내고 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.147-155
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• 2002

This paper describes RF front-end transceiver chipset for the dual-mode operation of PCS-Korea and IMT-2000. The transceiver chipset has been implemented in a $0.25\mutextrm{m}$ single-poly five-metal CMOS technology. The receiver IC consists of a LNA and a down-mixer, and the transmitter IC integrates an up-mixer. Measurements show that the transceiver chipset covers the wide RF range from 1.8GHz for PCS-Korea to 2.1GHz for IMT-2000. The LNA has 2.8~3.1dB NF, 14~13dB gain and 5~4dBm IIP3. The down mixer has 15.5~16.0dB NF, 15~13dB power conversion gain and 2~0dBm IIP3. The up mixer has 0~2dB power conversion gain and 6~3dBm OIP3. With a single 3.0V power supply, the LNA, down-mixer, and up-mixer consume 6mA, 30mA, and 25mA, respectively.