• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.6
• /
• pp.719-727
• /
• 2016

This paper proposes a unified medium access control (MAC) design methodology and presents the implementation of the IEEE 802.11ac down-link multi-user multi-input and multi-output wireless local area network MAC using the proposed design methodology. The proposed methodology employs unified code for both network simulation and system implementation. Because the unified code closely relates these two processes, the performance of the implemented MAC system can be estimated before implementation. The MAC architecture for an access point implemented using the proposed design methodology is verified on an ARM-based platform, and it is applied to a 65 nm CMOS library.

• Journal of Information Processing Systems
• /
• v.7 no.2
• /
• pp.321-340
• /
• 2011

In this article, the current technological state of OPC (Openness, Productivity, and Collaboration; formerly "OLE for Process Control") standards and the problem statement of these OPC standards are discussed. The development of an OPC clientserver framework for monitoring and control systems is introduced by using the new OPC Unified Architecture (UA) specifications, Service Oriented Architecture (SOA), web services, XML, etc. The developed framework in turn minimizes the efforts of developers in learning new techniques and allows system architects and designers to perform dependency analysis on the development of monitoring and control applications. The potential areas of the proposed framework and the redundancy strategies to increase the efficiency and reliability of the system are also represented according to the initial results from the system that was developed by the Visual Studio 2008 and OPC UA SDK.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.399-400
• /
• 2008

This paper presents a new architecture of unified IP/IT/IQ/MC circuit for H.264 decoder based on operation sharing and efficient scheduling. The resultant circuit based on the proposed architecture uses only 12 adders and 1 multiplier. We further reduced the circuit size by sharing buffers. Our circuit consists of 47,810 gates and operates at the maximum operating frequency of 117MHz with 130nm standard cells.

• Proceedings of the Korea Society for Industrial Systems Conference
• /
• 2002.11a
• /
• pp.136-160
• /
• 2002

Most important to financial institutions is to provide well designed and built services to the customers by accessing their core bank systems and affiliated systems in their partners. This will be essential to introduce new products and services and still be able to count on legacy and collaborative affiliated systems. Winning the war on such service competitions among financial institutions is attainable by seizing the "e-bank" opportunities in B2Bi and CRM (Customer Relationship Management). Such application integrations among systems and "e-bank" services need to be available in the new IT environment. In this article, an If and service architecture adopting unified e-business services platform is proposed. This architecture is able to achieve application integrations among legacy, affiliated, and e-business systems and services. We derive an architecture in unified e-business services platform by investigating current and future e-business services platforms involved in domestic and global international banks. Several financial interchange standards which are involved in B2B business of e-procurement, e-placement, e-payment are also investigated.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.10 no.8
• /
• pp.1970-1976
• /
• 2009

It is more emphasized on the software architecture recently, as the scale of a software becomes huge and the need of the software management becomes more dynamic. Software architecture is a representation of structures of software framework just like the blueprint of building architecture. In order to describe software components and their relationships accurately and entirely, software architecture is documented in some different views, by using of modeling tools. UML(Unified Modeling Language) is a software modeling tool recently used for documentation of software and as well as software architecture. Nevertheless, what we have to agree with is that UML is not easy to use and its standard changed continuously. And also the documentation with UML is found some burden because of its difficulties in learning and using. This inconvenience enforces us to purchase and use commercial tool for UML. The study introduces the architecture views refined from 4+1 Views for architecture design and shows how to represent architecture views for software architecture. Especially, we simplifies UML diagrams for the purpose of focusing on architecture views and facile manipulation. At the end, we add the evaluation on the refined architecture views as well as refined UML diagram.

• Journal of the Korean Institute of Telematics and Electronics S
• /
• v.36S no.11
• /
• pp.34-43
• /
• 1999

A high-speed image processor (HIP) is implemented for a high-speed multi-function peripheral. HIP has a binarization architecture with unified data path. It has the pixel-by-pixel pipelined processing to minimize size of the external memory. It performs pre-processing such as shading correction, automatic gain control (AGC), and gamma correction, and also drives external CCD or CIS modules. The pre-processed data can be enlarged or reduced. Various binarizatin algorithms can be processed in the unified archiecture. The embedded binarization algorithms are simple thresholding, high pass filtering, dithering, error diffusion, and thershold modulated error diffusion. These binarization algorithms are unified based on th threshold modulated error diffusion. The data path is designed to share the common functional block of the binarization algorithms. The complexity of the controls and the gate counts is greatly reduced with this novel architecture.

• Journal of architectural history
• /
• v.18 no.1
• /
• pp.7-29
• /
• 2009

In understranding the essence of the Korea traditional Architecture, it is important to consider the jointing methods of architectural members, architectural technologies, etc. Especially the purpose of this study is understanding on the Jointing Method of Wooden Members in the period of Unified Silla Architecture. It's conclusion is summarized as follows. 1. A section of column has very close to do with the foundation stone. The structures of foundation stone and column are generally concluded by butt joint, arrow-head joint, housed joint by Grang-e method. Judu is structured by arrow-head joint And, in general, beam is structured by Sagaematchum Chumcha and sagaljudu of Don direction. At the head of Pyungju and the body of Goju, Changbang is structed by Jangbumachum with arrow-head joint or by jumukchang-machum. Also, it is surmised that Gyisoseum and Anssolim methods had been applied to columns from former ages. The example can be found at Bagjae Mireuksaji stone pagoda. Bagjae Mireuksaji stone pagoda taking wooden-pagoda form adopts Gyisoseum and Anssolim methods. We can also find such a sort of methods from other stone constructions like Budo, etc. 2. Injahwaban is structured by short Changbumachum with arrowed-head joint at upper members, and by Anjangmachum at the lower part. This sort of Gongpo style can be seen in the mural painting of tomb of Koguryo and in Buplyungsa, Buplyunsa, Bupkisa-located in Japan, which are influenced by Bakjae or Unified Silla. It is considered that at the end of the late United Silla, Injawhaban had been replaced with Chumcha and Soro on the Pyungbang under influence of Dapo style from China.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.401-402
• /
• 2008

This paper presents an efficient architecture of unified transform and quantization circuit for H.264/JPEG CODEC. The proposed unified transform circuit shares adders required for all transform operations. The proposed unified quantization circuit uses four multipliers. Our transform circuit and quantization circuit consist of 33,711 gates and 9,650 gates respectively. The maximum operating frequency is 100MHz with 130nm standard cells.

• Journal of IKEEE
• /
• v.19 no.3
• /
• pp.392-399
• /
• 2015

This paper proposes a unified $4{\times}4$ transform architecture for HEVC and VP9 codec to reduce hardware size. It performs HEVC $4{\times}4$ IDCT, HEVC $4{\times}4$ IDST, VP9 $4{\times}4$ IDCT, and VP9 $4{\times}4$ IADST in a unified hardware. HEVC $4{\times}4$ IDCT and VP9 $4{\times}4$ IDCT have same IDCT computation except for the scales of coefficients. Similarly, HEVC $4{\times}4$ IDST and VP9 $4{\times}4$ IADST have same IDST computation except for the scales of coefficients. Furthermore, IDCT and IDST have quite a lot of similarity, so they can share some hardwares in common. So the proposed hardware performs all 4 operations in a unified hardware, where each operation has its own multiplication coefficients with shared butterfly adders. The synthesized block in 0.18 um technology is 6,679 gates, and the gate count is reduced by 25.3% in comparison with conventional designs.

• Proceedings of the IEEK Conference
• /
• 1998.10a
• /
• pp.135-138
• /
• 1998

In this paper, we propose an software architecture for home network gateway set-top-box that supports the connectivity between various consumer devices and the Internet simultaneously. To improve the scalability of the software, the proposed architecture uses the abstracted protocol driving structure, and to enhance the user-friendliness, the unified device access and management user interface is implemented using web technology. A prototype for the proposed architecture is implemented for evaluating the usability under the home network test bed.