• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1237-1241
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• 2003

In this paper, we report a novel RF-MEMS packaging technology with lightweight, small size, and short electric path length. To achieve this goal, we used the ultra thin silicon substrate as a packaging substrate. The via holes lot vortical feed-through were fabricated on the thin silicon wafer by wet chemical processing. Then, via holes were filled and micro-bumps were fabricated by electroplating. The packaged RF device has a reflection loss under 22 〔㏈〕 and a insertion loss of -0.04∼-0.08 〔㏈〕. These measurements show that we could package the RF device without loss and interference by using the vertical feed-through. Specially, with the ultra thin silicon wafer we can realize of a device package that has low-cost, lightweight and small size. Also, we can extend a 3-D packaging structure by stacking assembled thin packages.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2005.09a
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• pp.173-199
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• 2005

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.71-72
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• 2012

• Journal of Welding and Joining
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• v.29 no.1
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• pp.20-24
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• 2011

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.15-18
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• 2007

As the line width of the pattern become thin more and more, the accuracy of ultra-precision stage should be increased. Various type stages have been developed and used in fabrication phase and inspection lab. Furthermore the line with become several tens of nanometer recently. We need ultra high precision stage. In this paper a new type stage is proposed in order to reduce the deformation of working table. The table is supported by several flexure hinges and actuated by a PZT. The local deformation is analyzed and the vibratory motion is also examined by FEM package.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.4
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• pp.49-60
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• 2010

Semiconductor packages are increasingly moving toward miniaturization, lighter and high performance. Futhermore, packages become thinner. Thin packages will generate serious reliability problems such as warpage, crack and other failures. Reliability problems are mainly caused by the CTE mismatch of various package materials. Therefore, proper selection of the package materials and geometrical optimization is very important for controlling the warpage and the stress of the package. In this study, we investigated the characteristics of the warpage and the stress of several packages currently used in mobile devices such as CABGA, fcSCP, SCSP, and MCP. Warpage and stress distribution are analyzed by the finite element simulation. Key material properties which affect the warpage of package are investigated such as the elastic moduli, CTEs of EMC molding and the substrate. Geometrical effects are also investigated including the thickness or size of EMC molding, silicon die and substrate. The simulation results indicate that the most influential factors on warpage are EMC molding thickness, CTE of EMC, elastic modulus of the substrate. Simulation results show that warpage is the largest for SCSP. In order to reduce the warpage, DOE optimization is performed, and the optimization results show that warpage of SCSP becomes $10{\mu}m$.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.2
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• pp.31-43
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• 2019

In this study, polymer elastic bumps were fabricated for the flexible electronic package flip chip bonding and the viscoelastic and viscoplastic behavior of the polymer elastic bumps according to the temperature and load were analyzed using FEM and experiments. The polymer elastic bump is easy to deform by the bonding load, and it is confirmed that the bump height flatness problem is easily compensated and the stress concentration on thin chip is reduced remarkably. We also develop a spiral cap type and spoke cap type polymer elastic bump of $200{\mu}m$ diameter to complement Au metal cap crack phenomenon caused by excessive deformation of polymer elastic bump. The proposed polymer elastic bumps could reduce stress of metal wiring during bump deformation compared to metal cap bump, which is completely covered with metal wiring because the metal wiring on these bumps is partially patterned and easily deformable pattern. The spoke cap bump shows the lowest stress concentration in the metal wiring while maintaining the low contact resistance because the contact area between bump and pad was wider than that of the spiral cap bump.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.2
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• pp.7-15
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• 2012

Semiconductor packages are increasingly moving toward miniaturization, lighter and multi-functions for mobile application, which requires highly integrated multi-stack package. To meet the industrial demand, the package and silicon chip become thinner, and ultra-thin packages will show serious reliability problems such as warpage, crack and other failures. These problems are mainly caused by the mismatch of various package materials and geometric dimensions. In this study we perform the numerical analysis of the warpage deformation and thermal stress of 4-layer stacked FBGA package after EMC molding and reflow process, respectively. After EMC molding and reflow process, the package exhibits the different warpage characteristics due to the temperature-dependent material properties. Key material properties which affect the warpage of package are investigated such as the elastic moduli and CTEs of EMC and PCB. It is found that CTE of EMC material is the dominant factor which controls the warpage. The results of RSM optimization of the material properties demonstrate that warpage can be reduced by $28{\mu}m$. As the silicon die becomes thinner, the maximum stress of each die is increased. In particular, the stress of the top die is substantially increased at the outer edge of the die. This stress concentration will lead to the failure of the package. Therefore, proper selection of package material and structural design are essential for the ultra-thin die packages.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.8
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• pp.758-763
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• 2006

We has been studied the thin film encapsulation effect for organic light-emitting diodes (OLED). To evaluate the passivation properties of the passivation layer materials, we have carried out the fabrication of green light emitting diodes with ultra violet(UV) light absorbing polymer resin, $SiO_2,\;and\;SiN_x$, respectively. From the measurement results of shrinkage properties according to the exposure time to the atmosphere, we found that $SiN_x$ thin film is the best material for passivation layer. We have investigated the emission efficiency and life time of OLED device using the package structure of $OLED/SiN_x/polymer$ resin/Al/polymer resin. The emission efficiency of this OLED device was 13 lm/W and life time was about 2,000 hours, which reach 95 % of the performance for the OLED encapsulated with metal.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1703-1705
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• 2007

Before the ultra-violet glue encapsulation, the research evaporated LiF thin film on device surface to be the extra packaging layer for improving the lifetime of organic light-emitting diode. The formula of UV glue was specially developed. We found 100 nm LiF is the optimum thickness. The best lifetime obtained by using LiF and special UV glue is 2.4 times longer than those by commercial UV glue.