• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.567-568
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• 2008

In this paper, we proposed the design on LNA for $3{\sim}5\;GHz$ frequency with Using $0.18{\mu}m$CMOS technology. The LNA gain is 12-15 dB, and noise figure is lower than 5 dB and Input/output matching is lower than 10 dB in frequency range from 3 GHz to 5 GHz. The topology, which common source output of cascode is reduced noise figure and improved gain. Input common gate amplifier extend LNA's bandwidth.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.9
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• pp.1045-1050
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• 2008

In this paper presents a CMOS RF receiver for IR-UWB wireless communications is presented. The impulse radio based UWB receiver adopts the non-coherent demodulation that simplifies the receiver architecture and reduces power consumption. The IR-UWB receiver consists of LNA, envelop detector, VGA, and comparator and the receiver including envelope detector, VGA, and comparator is fabricated on a single chip using $0.18{\mu}m$ CMOS technology. The measured sensitivity of IR-UWB receiver is down to -70 dBm and the BER $10^{-3}$, respectively at data rate 1 Mbps. The current consumption of IR-UWB receiver except external LNA is 5 mA at 1.8 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.754-759
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• 2016

A transformer feedback low-noise amplifier (LNA) is implemented in a standard $0.18{\mu}m$ CMOS process, which exploits drain-to-gate transformer feedback technique for wideband input matching and operates across entire 3~5 GHz ultra-wideband (UWB). The proposed LNA achieves power gain above 9.5 dB, input return loss less than 15.0 dB, and noise figure below 4.8 dB, while consuming 8.1 mW from a 1.8-V supply. To the authors' knowledge, drain-to-gate transformer feedback for wideband input matching cascode LNA is the first adopted technique for UWB application.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.539-540
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• 2008

This paper presents an ultra-wideband (UWB) CMOS low noise amplifier (LNA) topology that operates in 3.1-10.6GHz band. The common gate structure provides wideband input matching and flattens the passband gain. The proposed UWB amplifier is implemented in 0.18 um CMOS technology for lower band operation mode. Simulation shows a minimum NF of 2.35 dB, a power gain of $18.3{\sim}20\;dB$, better than -10 dB of input and output matching, while consuming 16.4 mW.

• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.7-11
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• 2009

An Ultra-WideBand(UWB) Low-Noise Amplifier(LNA) is proposed and is implemented in a $0.18-{\mu}m$ CMOS technology. The proposed UWB LNA provides excellent wideband characteristics by combining a High-Pass Filter (HPF) with a conventional resistive-loaded LNA topology. In the proposed UWB LNA, the bell-shaped gain curve of the overall amplifier is much less dependent on the frequency response of the HPF embedded in the input stage. In addition, the adoption of fewer on-chip inductors in the input matching network permits a lower noise figure and a smaller chip area. Measurement results show a power gain of + 10 dB and an input return loss of more than - 9 dB over 2.7 to 6.2 GHz, a noise figure of 3.1 dB at 3.6 GHz and 7.8 dB at 6.2 GHz, an input PldB of - 12 dBm, and an IIP3 of - 0.2 dBm, while dissipating only 4.6 mA from a 1.8-V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.2 s.93
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• pp.139-143
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• 2005

In this paper, we propose the design on LNA and Down-mixer for MB-OFDM UWB using $0.18\;{\mu}m$ CMOS. LNA, Down-mixer design result shows that it covers the frequency range ken 3 GHz to 5 GHz. The LNA gain is larger than 12.8 dB, and noise figure about 2.6 dB. Double balanced differential down-mixer is designed less than 2 dB gainflatness, and it has over 30 dB LO leakage, feedthrough characteristics.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.1
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• pp.117-122
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• 2006

A CMOS LNA based on a single-stage cascode configuration is designed for MB-OFDM ultra-wide band(UWB) systems. Wideband($3.1GHz\~4.9GHz$) input matching is performed using a simple bandpass filter to minimize the chip size and the noise figure degradation. The simulation results using $0.18{\mu}m$ CMOS process parameters show a power gain of 9.7dB, a 3dB band width of $2.1GHz\~7.1GHz$, a minimum NF of 2dB, an IIP3 of -2dBm. better than -11.8dB of input matching while occupying only $0.74mm^2$ of chip area. It consumes 25.8mW from a 1.8V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.7
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• pp.657-663
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• 2009

A fully integrated single ended IR-UWB receiver is implemented using 0.18 ${\mu}m$ CMOS technology. The UWB receiver adopts the non-coherent architecture, which simplifies the RF architecture and reduces power consumption. The receiver consists of single-ended 2-stage LNAs, S2D, envelope detector, VGA, and comparator. The measured results show that sensitivity is -80.8 dBm at 1 Mbps and BER of $10^{-3}$. The receiver uses no external balun and the chip size is only $1.8{\times}0.9$ mm. The consumed current is very low with 13 mA at 1.8 V supply and the energy per bit performance is 23.4 nJ/bit.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.277-282
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• 2008

A fully integrated inductorless CMOS impulse radio ultra-wideband (IR-UWB) receiver is implemented using $0.18\;{\mu}m$ CMOS technology for 3-5 GHz application. The UWB receiver adopts the non-coherent architecture, which removes the complexity of RF architecture and reduces power consumption. The receiver consists of inductorless differential three stage LNA, envelope detector, variable gain amplifier (VGA), and comparator. The measured sensitivity is -70 dBm in the condition of 5 Mbps and BER of $10^{-3}$. The receiver chip size is only $1.8\;mm\;{\times}\;0.9\;mm$. The consumed current is 15 mA with 1.8 V supply.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.4 s.119
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• pp.408-415
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• 2007

A switched-gain controlled LNA is designed and implemented in 0.18 um CMOS technology for $3.1{\sim}4.8\;GHz$ UWB system. In high gain mode, measurement shows a power gain of 12.5 dB, an input IP3 of 0 dBm, while consuming only 8.13 mA of current. In low gain mode, measurement shows a power gain of -8.7 dB, an input IP3 of 9.1 dBm, while consuming only 0 mA of current.