• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11A
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• pp.1053-1058
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• 2006

In this paper, We proposed a efficient OSA(Optical Sub-Assembly) packaging method in use 1.31/1.49um bi-directional hybrid-integrated PLC chip for low-cost OSA in optical access network system applications as GE-PON in FTTH. Fabricated OSA with passive optical fiber alignment and nonhermetic plastic package method and measured optical coupling efficiency and electric-optical characteristics. Its performance is feasible to satisfy the GE-PON ONU specifications with the results as less than 0.5dB coupling losses within 40um alignment of z-axis and less than -24dBm sensitivity. It also has good temperature characteristics to sustain optical output power more than 1.5mW and 10dB extinction ratio, less than 0.3dB tracking error.

• Proceedings of the KIEE Conference
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• 2007.10a
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• pp.483-484
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• 2007

In this paper, we describe a chip design technique for instrumentation amplifier using a nested-chopping technique. Conventional chopping technique uses a pair of chopper, but nested chopping technique uses two pairs of chopper to reduce residual offset and 1/f noise. The inner chopper pair removes the 1/f noise, while the outer chopper pair reduces the residual offset. Our instrumentation amplifier using a nested chopping technique has residual offset under 100 nV. We also implement very low frequency filter. Since this filter needs very large RC time constant, we use a technique named 'diode connected PMOS' to increase R with small die area. The total power consumption is 3.1 mW at the supply voltage of 3.3V with the 0.35um general CMOS technology. The die area of implemented chip was $530um{\times}300um$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.3
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• pp.75-85
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• 2009

This work proposes a 13b 100MS/s 0.13um CMOS ADC for 3G communication systems such as two-carrier W-CDMA applications simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs a four-step pipeline architecture to optimize power consumption and chip area at the target resolution and sampling rate. Area-efficient high-speed high-resolution gate-bootstrapping circuits are implemented at the sampling switches of the input SHA to maintain signal linearity over the Nyquist rate even at a 1.0V supply operation. The cascode compensation technique on a low-impedance path implemented in the two-stage amplifiers of the SHA and MDAC simultaneously achieves the required operation speed and phase margin with more reduced power consumption than the Miller compensation technique. Low-glitch dynamic latches in sub-ranging flash ADCs reduce kickback-noise referred to the differential input stage of the comparator by isolating the input stage from output nodes to improve system accuracy. The proposed low-noise current and voltage references based on triple negative T.C. circuits are employed on chip with optional off-chip reference voltages. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.70LSB and 1.79LSB, respectively. The ADC shows a maximum SNDR of 64.5dB and a maximum SFDR of 78.0dB at 100MS/s, respectively. The ABC with an active die area of $1.22mm^2$ consumes 42.0mW at 100MS/s and a 1.2V supply, corresponding to a FOM of 0.31pJ/conv-step.

• 전자공학회논문지 IE
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• v.47 no.2
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• pp.13-20
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• 2010

This paper describes a current mode PWM DC-DC converter IC for battery charger and supply power converter for portable electronic devices. The maximum supply voltage of IC is 40[V] and 2.8[V]~330[V] DC input power is converted to higher or programmed DC voltage according to external resistor ratio or wire winding ratio of transformer. The maximum supply output current is 3[A] over and voltage error of output node is within 3[%]. The whole circuit needed current mode PWM DC-DC converter circuit is designed. The package dimensions and number of external parts are minimized in order to get a smaller hardware size. The power consumption is smaller then 1[mW] at stand by period with supply voltage of 3.6[V] and maximum energy conversion efficiency is about 86[%]. This device has been designed in a 0.6[um] double poly, double metal 40[V] CMOS process and whole chip size is 2100*2000 [um2].

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.5
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• pp.25-33
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• 2011

This work proposes a skinny-type 10b 50MS/s 0.13um CMOS three-step pipeline ADC for CIS applications. Analog circuits for CIS applications commonly employ a high supply voltage to acquire a sufficiently acceptable dynamic range, while digital circuits use a low supply voltage to minimize power consumption. The proposed ADC converts analog signals in a wide-swing range to low voltage-based digital data using both of the two supply voltages. An op-amp sharing technique employed in residue amplifiers properly controls currents depending on the amplification mode of each pipeline stage, optimizes the performance of op-amps, and improves the power efficiency. In three FLASH ADCs, the number of input stages are reduced in half by the interpolation technique while each comparator consists of only a latch with low kick-back noise based on pull-down switches to separate the input nodes and output nodes. Reference circuits achieve a required settling time only with on-chip low-power drivers and digital correction logic has two kinds of level shifter depending on signal-voltage levels to be processed. The prototype ADC in a 0.13um CMOS to support 0.35um thick-gate-oxide transistors demonstrates the measured DNL and INL within 0.42LSB and 1.19LSB, respectively. The ADC shows a maximum SNDR of 55.4dB and a maximum SFDR of 68.7dB at 50MS/s, respectively. The ADC with an active die area of 0.53$mm^2$ consumes 15.6mW at 50MS/s with an analog voltage of 2.0V and two digital voltages of 2.8V ($=D_H$) and 1.2V ($=D_L$).

• Proceedings of the IEEK Conference
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• summer
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• pp.82-85
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• 2004

This paper proposes an advanced circuit for the capacitive type fingerprint sensor signal processing and an effective isolation structure for minimizing an electrostatic discharge(ESD) influence and for removing a signal coupling noise of each sensor pixel. The proposed detection circuit increases the voltage difference between a ridge and valley about $80\%$ more than old circuit. The test chip is composed of $160\;\times\;192$ array sensing cells $(9,913\times11,666\;um^2).$ The sensor plate area is $58\;\times\;58\;um^2$ and the pitch is 60um. The image resolution is 423 dpi. The chip was fabricated on a 0.35um standard CMOS process. It successfully captured a high-quality fingerprint image and performed the registration and identification processing. The sensing and authentication time is 1 sec(.) with the average power consumption of 10 mW at 3.0V. The reveal ESD tolerance is obtained at the value of 4.5 kV.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.14 no.3
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• pp.189-196
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• 1989

In this paper, BICMOS gate array technology that has CMOS devices for logic applications and bipolar devices for driver applications is presented. An optimized poly gate p-well CMOS process is chosen to fabricate the BICMOS gate array system and the basic concepts to design these devices are to improve the characteristics of bipolar & CMOS device with simple process technology. As the results hFE value is 120(Ic=1mA) for transistor, and there is no short channel effects for CMOS devices which have Leff to 1.25um and 1.35um for n-channel, respectively, 0.8nx gate delay time of 41 stage ring oscillators is obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.62-68
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• 2010

This work proposes a 10b 100MS/s DAC based on a segmented local matching technique primarily for small chip area. The proposed DAC employing a segmented current-steering structure shows the required high linearity even with the small number of devices and demonstrates a fast settling behavior at resistive loads. The proposed segmented local matching technique reduces the number of current cells to be matched and the size of MOS transistors while a double-cascode topology of current cells achieves a high output impedance even with minimum sized devices. The prototype DAC implemented in a 0.13um CMOS technology occupies a die area of $0.13mm^2$ and drives a $50{\Omega}$ load resistor with a full-scale single output voltage of $1.0V_{p-p}$ at a 3.3V power supply. The measured DNL and INL are within 0.73LSB and 0.76LSB, respectively. The maximum measured SFDR is 58.6dB at a 100MS/s conversion rate.

• Journal of the Korean Society of Visualization
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• v.11 no.2
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• pp.41-45
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• 2013

Two-photon microscopy (TPM) is minimally-invasive 3D fluorescence microscopy based on nonlinear excitation, and TPM can visualize cellular structures based on auto-fluorescence. Line-scanning TPM is one of high-speed TPM methods without sacrificing the image resolution by using spatial and temporal focusing. In this paper, we developed line-scanning TPM based on spatial and temporal focusing for auto-fluorescence imaging by exciting the tryptophan. Laser source for this system was an optical parametric oscillator (OPO) and it made near 570 nm femtosecond pulse laser. It had 200fs pulse width and 1.72 nm bandwidth, so that the achievable depth resolution was 2.41um and field of view (FOV) is 10.8um. From the characterization, our system has 3.0 um depth resolution and 12.3 um FOV. We visualized fixed leukocyte cell sample and compared with point scanning system.

• The Korean Journal of Zoology
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• v.37 no.3
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• pp.385-408
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• 1994

출생후 0일. 7일. 14일 및 21일 그리고 성체의 흰쥐 전뇌 기저부의 내측중격핵, 수직 및 수평 대각 Broca대 거대세포 시삭전핵 그리고 복부담창구에서 신경성장인자수용체 (nerv-growth 배ctor receptor, NGFr)에 면역반응을 보이는 신경조직과 세포의 분화를 면역조직화학적 및 전자현미경적 방법을 이용하여 조사하였다. 출생후 초기와 성체에서 신경세포 원형질막 뿐만 아니라 세포질에서 NGFr 면역반응이 확인되었다. 그러나 성체에서 신경세포 원형질 막에서의 면역반응은 관찰되지 않았다. 특히 NGFr 면역반응은 골지 부위에서 보였고, 점상의 면역반응물들이 세포체의 세포질과 수상돌기에 소수 분산 분포하였다. 뇌 기저부의 NGFr 면역반응 신경세포들은 뇌 크기의 증대와 뇌 조직의 분화에 따라 점차 수적 증가를 보였다. 이 NGFr 면역반응 신경세포들은 세포의 모양과 세포체의 장 .단축의 비에 따라 6가지 형. 즉 1) 원형. 2) 타원형. 3) 세장형, 4) 방추형, 5) 삼각형, 6) 다각형으로 분류되었다. 전뇌 기저 핵에서 원형과 난형신경세포들의 출현율은 출생후 0일에서 높았으나 성체로 되면서 감소된 반면, 세장형. 방추형, 삼각형 그리고 다각형신경세포들의 출현율은 출생후 0일에서는 낮았으나 성체로 되면서 증가하였다. 모든 핵들에서 NGFr 면역반응 신경세포체의 부피는 출생후 0일에 759-1,640 Um3로 제일 작았으며, 수직 대각 Broca대와 복부담창구에서는 출생후 14일에 각각 5 107 7.385 Um3 그리고 내측중격핵, 수평 대각 Broca대, 거대세포 시삭전핵에서는 출생후 21일에 각각 4,705, 6,061, 6,412 Um3로 최대치를 보였다. 그후 성체로 되면서 모든 핵에서 1,893-3,464 $\mu$m3로 다시 감소하였다. 전자현미경적 관찰에서 출생후 21일된 흰쥐 수평 대각 Broca대에서 NGFr 면역반응은 세포체와 수상돌기의 원형질막 그리고 세포체내에서는 골지체, 다소포성소체 및 조면소포체에서 관찰되었다. 이 결과들로 미루어 NGFr은 출생후 발생단계와 성체의 횐쥐 전뇌 기저부에서 신경세포의 분화와 분포에 관계되는 것으로 생각된다.