• The Transactions of the Korean Institute of Power Electronics
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• v.12 no.6
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• pp.441-448
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• 2007

To enhance the competitive edge of the material cost, IP(Integrated Power) Board form of inverter circuit is widely used in large area LCD TV(Greater than or equal to 40 in.). This scheme is Two Stage System and one inverter drives multi-lamp in a parallel circuit. This paper analyzes the conventional IP Board inverter controlled with Pulse Width Modulation (PWM), and its problems such as serious hard switching and excessive circulating energy can be solved by a proposed Pulse Count Modulation (PCM) scheme. To confirm the validity and superiority of the proposed system, theoretical analysis and experimental results are presented.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.3
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• pp.81-87
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• 2015

In order to effectively protect electrical and electronic circuits which are extremely susceptible to lightning surges, multi-stage surge protection circuits are required. This paper presents the operational characteristics of the two-stage hybrid surge protection circuit in extra-low voltage DC power lines. The hybrid surge protective device consists of the gas discharge tube, transient voltage suppressor, and series inductor. The response characteristics of the proposed hybrid surge protective device to combination waves were investigated. As a result, the proposed two-stage surge protective device to combination wave provides the tight clamping level of less than 50V. The firing of the gas discharge tube to lightning surges depends on the de-coupling inductance and the rate-of-change of the current flowing through the transient voltage suppressor. The coordination between the upstream and downstream components of the hybrid surge protective device was satisfactorily achieved. The inductance of a de-coupler in surge protective circuits for low-voltage DC power lines, relative to a resistance, is sufficiently effective. The voltage drop and power loss due to the proposed surge protective device are ignored during normal operation of the systems.

• Proceedings of the KIEE Conference
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• 1999.07g
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• pp.3181-3183
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• 1999

A CMOS two-stage oscillator applicable to requiring in- and quadrature-phase components such as RF and data retiming applications are presented using phase-look-ahead technique. This paper clearly describes the operation principle of the presented two-stage oscillator and the principle can be also applicable to the high speed high speed divide-by-two is usually used for prescaler of the frequency synthesizer. Also, the sucessful oscillation of the proposed oscillator using PLA is confirmed through the experiment. The test vehicle is designed using 0.8 ${\mu}m$ N-well CMOS process and it has a maximum 914MHz oscillation showing -75dBclHz phase noise at 100kHz offset with single 2V supply.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.369-372
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• 2002

To remedy both the degradation and saturation of the output voltages in the modified Dickson pump, a new multistage charge pump circuit is presented in this paper. Here using PMOS charge-transfer switches instead of NMOS ones eliminates the necessity of diode-configured output stage in the modified-Dickson pump, achieving the improved voltage pumping gain and its output voltages proportional to the stage numbers. Measurement indicates that VOUT/3VDD of this new pump circuit with two stages reaches to a value as high as 0.94V even with low VDD=1.0 V, strongly addressing that this scheme is very favorable at low-voltage memory applications.

• ETRI Journal
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• v.24 no.3
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• pp.190-196
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• 2002

This paper presents millimeter wave monolithic microwave integrated circuit (MMIC) low noise amplifiers using a $0.15{\mu}m$ commercial pHEMT process. After carefully investigating design considerations for millimeter-wave applications, with emphasis on the active device model and electomagnetic (EM) simulation, we designed two single-ended low noise amplifiers, one for Q-band and one for V-band. The Q-band two stage amplifier showed an average noise figure of 2.2 dB with an 18.3 dB average gain at 44 GHz. The V-band two stage amplifier showed an average noise figure of 2.9 dB with a 14.7 dB average gain at 65 GHz. Our design technique and model demonstrates good agreement between measured and predicted results. Compared with the published data, this work also presents state-of-the-art performance in terms of the gain and noise figure.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.85-96
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• 2000

It is necessary that fully differential operational amplifier circuit should drive an external load in the VLSI design such as SCF(Switched Capacitor Filter), D/A Converter, A/D Converter, Telecommunication Circuit and etc. The conventional CMOS operational amplifier circuit has many problems according to CMOS technique. Firstly, Capacity of large loads are not able to operate well. The problem can be solve to use class AB stages. But large loads are operate a difficult, because an element of existing CMOS has a quadratic functional relation with input and output voltage versus output current. Secondly, Whole circuit of dynamic range decrease, because a range of input and output voltages go down according as increasing of intergration rate drop supply voltage. The problem can be improved by employing fully differential operational amplifier using differential output stage with wide output swing. In this paper, we proposed new current mirror has large output impedance and good current matching with input an output current and compared with characteristics for operational amplifier using cascoded current mirror. To obtain large output swing and low power consumption we suggest a fully differential operational amplifier. The circuit employs an output stage composed new current mirror and two amplifier stage. The proposed circuit is layout and circuit of capability is inspected through simulation program(SPICE3f).

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.46-52
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• 1991

A new signal process circuit using two ISFETs as the input devices of the MOS differential amplifier stage for an ISFET biosensor has been developed. One chip integration of the newly developed signal process circuit, ISFETs and a Pt quasi-reference electrode has been carried out according to modified LOCOS p-well CMOS process. The fabricated chip showed gains of 0.8 and 1.6, good liniarity in the input-output relationship and very small power dissipation, 4mW. The chip was applied to realize a urea sensor by forming an immobilized urease membrane, using lift-off technique. on the gate of an ISFET. The urea sensor chip showed stable responses in a wide range of urea concentrations.

• Proceedings of the Optical Society of Korea Conference
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• 1990.02a
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• pp.136-140
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• 1990

A hybrid wideband amplifier having bandwidth from 5MHz to 2000MHz with a gain of 10db$\pm$3dB is designed and implemented by using a lossy matched network and GaAs FET. The implemented amplifier circuit operates as a capacitor-resistor(C-R) coupled amplifier circuit in the low frequency range (below 800 MHz) in which {{{{ LEFT $\mid$ S_{21 } RIGHT $\mid$ }} for the GaAs FET is constant. It also operates as a lossless impedance matching circuit in the microwave frequency range in which S21 for the GaAs FET has a slope of approximately -6dB/octave. Using this configuration technique, Two stage GaAs FET amplifier implemented is measured to 10dB gain within a 3dB fluctuation over the frequency band from 5 to 2000MHz.

• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.135-138
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• 2001

In order to solve the problem of system efficiency reduced on account of two stage power conversion, we propose a series resonant full bridge inverter circuit for battery-fed microwave oven. This circuit has both a compact size and a light weight. Also, a frequency control adjusts power levels of the microwave oven. Operational principles are explained in detail. A proto-type inverter circuit with 1[kW] power consumption is built and tested for verifying the operation.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.179-185
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• 2005

This paper presents a novel circuit topology of a high efficiency single-phase power conditioner. This power conditioner is composed of time-sharing sinewave absolute pulse width modulated boost chopper with a bypass diode in the first power processing stage and time-sharing sinewave pulse width modulated full-bridge inverter in the second power processing stage operated by time-sharing dual mode pulse pattern control scheme. The unique operating principle of the two power processing stage with time-sharing dual mode sinewave modulation scheme is described with a design example. This paper proposes also a sinewave tracking voltage controlled soft switching PWM boost chopper with a passive auxiliary edge-resonant snubber. The new conceptual operating principle of this novel power conditioner related to new energy utilization system is presented and discussed through the experimental results.