• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.8
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• pp.1465-1470
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• 2006

This paper presents a design of low power CMOS LNA(Low Noise Amplifier) for 2.4 GHz ZigBee applications that is a promising international standard for short area wireless communications. The proposed circuit has been designed using TSMC $0.18{\mu}m$ CMOS process technology and two stage cascade topology by current reuse technique. Two stage cascade amplifiers use the same bias current in the current reused stage which leads to the reduction of the power dissipation. LNA design procedures and the simulation results using ADS(Advanced Design System) are presented in this paper. Simulation results show that the LNA has a extremely low power dissipation of 1.38mW with a supply voltage of 1.0V. This is the lowest value among LNAs ever reported. The LNA also has a maximum gain of 13.38dB, input return loss of -20.37dB, output return loss of -22.48dB and minimum noise figure of 1.13dB.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8C
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• pp.806-815
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• 2006

It is studied to design a low pass filter of the SRC(sample rate converter), which is used to change the sampling rate of digital signals such as in digital modulation and demodulation systems. The larger the conversion ratio of the sample rate becomes, the more signal processing is needed for the filter, which corresponds to the more complexity in circuit realization. Thus it is important to reduce the amount of signal processing for the case of high conversion ratio. In this paper it is presented a design method of a two-stage cascaded FIR filter, which proved to have reduced amount of signal processing in comparison with a conventional single-stage one. The reduction effect of signal processing turned out to be more noticeable for larger value of conversion ratio, for instance, giving down to 72% in complexity for the conversion ratio of 32. It has been shown that the reduction effect is dependent to specific combination of conversion ratios of the cascaded filters. So an exhaustive search has been performed in order to obtain the optimal combination for various values of the total conversion ratio. In this paper every filter is considered to be implemented in the form of a polyphase FIR filter, and its coefficients are determined by use of the Parks-McCllelan algorithm.

• Journal of electromagnetic engineering and science
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• v.11 no.2
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• pp.76-82
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• 2011

In this paper, a novel design for a dual-band negative group delay circuit (NGDC) is proposed. Composite right/left-handed (CRLH) ${\lambda}/4$ short stubs are employed as a dual-band resonator. A CRLH ${\lambda}/4$ short stub is composed of a typical transmission line element as the right-handed component and a high-pass lumped element section as the left-handed component. It is possible to simultaneously obtain open impedances at two separate frequencies by the combination of distinctive phase responses of the right/left-handed components. Negative group delay (NGD) can be obtained at two frequencies by using dual-band characteristics of the CRLH stub. In order to achieve a bandwidth extension, the proposed structure consists of a two-stage dual-band NGDC with different center frequencies connected in a cascade. According to the experiment performed, with wide-band code division multiple access (WCDMA) and worldwide interoperability for microwave access (WiMAX), NGDs of $-3.0{\pm}0.4$ ns and $-3.1{\pm}0.5$ ns are obtained at 2.12~2.16 GHz and 3.46~3.54 GHz, respectively.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.18 no.6 s.121
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• pp.674-679
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• 2007

In this paper, the size of the dual-mode microstrip ring resonator is reduced by adding four open stubs, and bandpass filters having 100 MHz bandwidth are designed at the center frequency of 2 GHz. The size of the ring resonator can be controlled by varying the capacitance of the stubs, and the bandpass filter can be designed in two cases, which are two combinations of the stubs. Two bandpass filters are designed and fabricated by using the two-stage bandpass filter circuit model of the proposed structure, and the measured results show good agreement with the simulated results.

• Journal of Drive and Control
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• v.17 no.2
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• pp.55-62
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• 2020

There are two types of IMV for MCV, the spool type and the poppet type. The spool type is used in the existing excavator MCV and easily meets large-capacity flow conditions, but has a flow force problem which affects the spool control. The poppet type stably blocks the flow and has excellent rapid response. However, the larger the capacity, the larger the diameter of the poppet needed, requiring a strong spring to withstand the oil pressure. In this study, a bi-directional three-stage IMV for MCV that can be used in medium and large hydraulic excavators was proposed. This is a poppet type, enabling bi-directional flow control and resolves the problem of proportional solenoid suction force limitation. To investigate the validity of the proposed valve, the system was mathematically modeled and the static and dynamic characteristics were investigated through the simulation using commercial software. It has been concluded that the reverse flow is possible in a regeneration circuit and that the proposed IMV can be used to perform various excavation modes.

• Journal of IKEEE
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• v.13 no.4
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• pp.57-62
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• 2009

In this paper, to implement PCS (Physical Coding Sublayer) of 10GBASE-R type, we present 2 stage pipeline 64b/66b Encoder/Decoder which operates at 156.25MHz standard specification and designed to minimize clock latency as possible as we can. The proposed circuit was designed based on Verilog hardware description language and measured for functional verification on VertexII-1000fg456 chip of Xilinx Inc.. Total equivalent gate count is 47,303 and estimated power consumption is 351mW at Vcc 3.3V.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1137-1140
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• 2002

A V-band low-noise amplifiers (LNA) based on the Millimeter-wave monolithic integrated circuit (MIMIC) technology were fabricated using high performance 0.1 $\mu\textrm{m}$ $\Gamma$-shaped pseudomorphic high electron mobility transistors (PHEMT＇s), coplanar waveguide (CPW) structures and the integrated process for passive and active devices. The low-noise designs resulted in a two-stage MIMIC LNA with a high S$\sub$21/ gain of 14.9 dB and a good matching at 60 ㎓. 20 dBm of IP3 and 3.9 dB of minimum noise figure were also obtained from the LNA. The 2-stage LNA was designed in a chip size of 2.3 ${\times}$1.4 mm$^2$by using 70 $\mu\textrm{m}$ ${\times}$2 PHEMT’s. These results demonstrate that a good low-noise performance and simultaneously with a high gain performance is achievable with GaAs PHEMT's in the 60 ㎓ band.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.321-328
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• 2008

In this paper, variable gain amplifier(VGA) with a gain slope controller has been proposed and verified by circuit simulations and measurements. The proposed VGA has a gain control, gain slope switch and variable gain range. The input source coupled pair with diode connected load is used for VGA gain stage. The gain slope controller with switch can control VGA gain slope. The proposed VGA is fabricated in $0.18{\mu}m$ CMOS process for multi -standard wireless receiver. The proposed two stage VGA consumes min. 2.0 mW to max. 2.6 mW in gain control range and gives input IP3 of -3.77 dBm and NF of 28.7 dB at 1.8 V power supply under -25 dBm, 1 MHz input. The proposed VGA has 37 dB(-16 dB $\sim$ 21 dB) variable gain range, and 8 dB gain range control per 0.3 V control voltage, and can provide variable gain, positive and negative gain slope control, and gain range control. This VGA characteristics provide design flexibility in multi-standard wireless receiver.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.6
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• pp.460-465
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• 2010

The interest is coming to be high, recently with depletion of the fossil fuel and with carbon dioxide exhaust limit about emittion, from a car of Internal combustion engine to Electric vehicle. AC-DC converter is necessary to battery charging which is an electric vehicle energy storage. Necessary conditions of the converter are necessary for wide output voltage range, high efficiency, high power factor etc. It is composed two stages for wide output voltage range and insulation. Preliminary stage uses LLC resonant converter and the after stage uses BOOST converter PFC circuit for being considered a power factor and confirmed experimentally.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.53-64
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• 2002

This paper describes a design of cryptographic processor that implements the AES (Advanced Encryption Standard) block cipher algorithm, "Rijndael". An iterative looping architecture using a single round block is adopted to minimize the hardware required. To achieve high throughput rate, a sub-pipeline stage is added by dividing the round function into two blocks, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. The round block is implemented using 32-bit data path, so each sub-pipeline stage is executed for four clock cycles. The S-box, which is the dominant element of the round block in terms of required hardware resources, is designed using arithmetic circuit computing multiplicative inverse in GF($2^8$) rather than look-up table method, so that encryption and decryption can share the S-boxes. The round keys are generated by on-the-fly key scheduler. The crypto-processor designed in Verilog-HDL and synthesized using 0.25-$\mu\textrm{m}$ CMOS cell library consists of about 23,000 gates. Simulation results show that the critical path delay is about 8-ns and it can operate up to 120-MHz clock Sequency at 2.5-V supply. The designed core was verified using Xilinx FPGA board and test system.