• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.302-302
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• 2000

This paper presents the measurement and correction of PCB alignment errors for PCB-manufacturing machines. The conventional PCB-manufacturing machine doesn't have enough accuracy to accommodate the demand for high-resolution circuit pattern and high-density mounting capacity of electronic chips. It is because of alignment errors of PCB loaded to the PCB-manufacturing machine. Therefore, this study focuses on the development of the system which is able to measure and correct alignment errors whit high-accuracy. An automatic optical inspection part measures the PCB alignment error using two cameras, and the high-accuracy 3-axis stage makes correct of these error. The operating system is run in the environment of Window 98 (or NT). Finally we implemented this system to PCB screen printer and PCB exposure system.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.102-106
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• 1999

We have designed and fabricated a four-bit shift register circuit using YBCO bicrystal junctions and experimentally tested its operations by a computer-controlled digital measurement set-up. Laser ablated YBCO thin films with clean surface were used in this work. The circuit consists of the shift register and two read SQUIDs placed next to each sides of the shift register. The SQUIDs were inductively coupled to the nearby shift register stages. A probe equipped with high speed coax lines were used in this experiment. The major obstacle in testing the circuit was the interference between the read SQUIDs and we solved the problem by finding the correct operation points of the SQUIDs from the simultaneously measured modulation curves. Loaded Data("1" or "0") were successfully shifted from a stage to the next one by a controlled current pulse injected to the bias lines located between the stages and the data shifts were correctly monitored by the read SQUIDs

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.1
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• pp.35-42
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• 2010

This paper presents the Two-stage LED Driving system using LLC resonant converter for LED lighting application. Due to the existence of the nonisolation DC/DC converter to control the LED current and the light intensity, the conventional three-stage LED Driving system has the problem of low power conversion efficiency. To solve this problem, a novel scheme without any nonisolation DC/DC converter is proposed, in which, the isolated DC/DC converter, e.g., LLC resonant converter in the paper, can perform the LED current control and stage, e.g., PFC stage and LLC stage, the efficiency can be significantly improved. Moreover, the cost and the volume of the whole LED driving system can be reduced compared to those of the conventional ones. The operational principle and the characteristics of the proposed scheme are presented. The proposed scheme is verified experimentally with a 45W output prototype LED driver.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.7
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• pp.1261-1266
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• 2017

A random and systematic jitter suppressed delay locked loop (DLL)-based clock generator with a delay-time voltage variance converter (DVVC) and an averaging circuit (AC) is presented. The DVVC senses the delay variance of each delay stage and generates a voltage. The AC averages the output voltages of two consecutive DVVCs to suppress the systematic and random delay variance of each delay stage in the VCDL. The DVVC and AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. In addition, a capacitor with a switch working effectively as a negative feedback function is introduced to reduce the variation of the loop filter output voltage. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.4
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• pp.384-394
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• 1999

This paper deals with a fixed frequency full-bridge inverter type DC-DC high-power converter with high frequency high voltage(HFHV) transformer-coupled stage, which operates under quasi-resonant ZVS transition priciple in spite of a wide PWM-based voltage regulation processing and largely-changed load conditions. This multi-resonant(MR) converter topology is composed of a series capacitor-connected parallel resonant tank which makes the most of parasitic circuit reactive components of HFHV transformer and two additional quasi-resonant pole circuits incorporated into the bridge legs. The soft-switching operation and practical efficacy of this new converter circuit using the latest IGBTs are actually ascertained through 50kV trially-produced converter system operating using 20kHz/30kHz high voltage(HV) transformers which is applied for driving the diagnostic HV X-ray tube load in medical equipments. It is proved from a practical point of view that the switching losses of IGBTs and their electrical dynamic stresses relating to EMI noise can be considerably reduced under a high frequency(HF) switching-based phase-shift PWM control process for a load setting requirements.

• 한국초전도학회:학술대회논문집
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• v.9
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• pp.133-133
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• 1999

We have fabricated and tested a simple circuit of the rapid single-flux-quantum(RSFQ) four-stage shift register using a single layer high-T$_c$ superconducting (HTS) YBa$_2Cu_3O_{7-x}$ (YBCO) thin film structure with 9 step-edge Josephson junctions. The circuit includes two read superconducting quantum interference devices(SQUID) and four stages. To establish a robust HTS RSFQ device fabrication process, we have focussed the reproducible process of sharp and straight step-edge formation as well as the ratio of film thickness to step height t/h. The spread of step-edge junction parameters was measured from each13 junctions with t/h=l/3, l/2, and 2/3 at various temperatures. We have demonstrated the simplified operation of the shift register at 65 K..

• Transactions on Electrical and Electronic Materials
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• v.18 no.5
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• pp.257-260
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• 2017

In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of $703{\mu}m^2$, ensuring that the proposed circuit is suitable for low-power applications.

• Journal of Power Electronics
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• v.18 no.3
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• pp.694-701
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• 2018

This paper proposes a new single-phase power converter topology for changing the frequency of AC voltage. The proposed single-phase frequency converter (SFC) includes a T-type multi-level power converter (TMPC), a frequency decoupling transformer (FDT) and a digital signal processor (DSP). The TMPC can convert a 60 Hz AC voltage to a DC voltage and then convert the DC voltage to a 50 Hz AC voltage. Therefore, the output currents of the two T-type power switch arms have 50 Hz and 60 Hz components. The FDT is used to decouple the 50 Hz and 60 Hz components. The salient feature of the proposed SFC is that only one power electronic converter stage is used since the functions of the AC-DC and DC-AC power conversions are integrated into the TMPC. Therefore, the proposed SFC can simplify both the power circuit and the control circuit. In order to verify the functions of the proposed SFC, a hardware prototype is established. Experimental results verify that the performance of the proposed SFC is as expected.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.232-238
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• 2008

In this paper, a wideband power efficient 2.2 GHz - 4.9 GHz Medium Power Amplifier (MPA), has been designed and fabricated using $0.8{\mu}m$ SiGe BiCMOS process technology. Passive elements such as parallel-branch spiral inductor, metal-insulator-metal (MIM) capacitor and three types of resistors are all integrated in this process. This MPA is a two stage amplifier with all matching components and bias circuits integrated on-chip. A P1dB of 17.7 dBm has been measured with a power gain of 8.7 dB at 3.4 GHz with a total current consumption of 30 mA from a 3 V supply voltage at $25^{\circ}C$. The measured 3 dB bandwidth is 2.7 GHz and the maximum Power Added Efficiency (PAE) is 41 %, which are very good results for a fully integrated Medium PA. The fabricated circuit occupies a die area of $1.7mm{\times}0.8mm$.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.630-634
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• 2004

This paper describes the design of a two stage 1V power supply SiGe Low Noise Amplifier operating at 5.25 GHa for 802.lla wireless LAN application. The achieved performance includes a gain of 17 ㏈, noise figure of 2.7㏈, reflection coefficient of 15 ㏈, IIP3 of -5 ㏈m, and 1-㏈ compression point of -14㏈m. The total power consumption of the circuit was 7 mW including 0.5mW for the bias circuit.