• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 하계학술대회 논문집 B
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• pp.986-989
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• 2002

This paper proposes a new single stage power factor correction (PFC) full bridge converter which operates at continuous conduction mode(CCM). The proposed single stage PFC consists of typical zero voltage switching(ZVS) full bridge DC/DC converter, two transformer auxiliary windings, and two small inductors, and two diodes. Neither additional active switch nor any control circuit are added for PFC resulting in very low cost. The proposed converter provides input power factor correction with CCM control and tight output voltage regulation. All switching devices are operated under ZVS with minimum voltage stress. Operation principle and analysis are explained and verified with computer simulation and experimental results on a 1.2kW, 100kHz prototype.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 A
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• pp.385-387
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• 1996

A novel two stage soft-switching ac-to-dc convener with power factor correction is proposed. The proposed convener provides zero-voltage-switching (ZVS) condition to main switch of boost pre-regulator without auxiliary switch. Comparing to the conventional two stage approach(ZVS-PWM boost rectifier followed by off-line ZVS dc-dc step down converter), the proposed approach is simple and reducing EMI noise problem. A new simple DC-linked energy feedback circuit provides zero-voltage-switching condition to boost pre-regulator without imposing additional voltage and current stresses and loss of PWM capability. Operational principle, analysis, control of the proposed converter together with the simulation results of 1KW prototype are presented.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2003년도 추계종합학술대회
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• pp.304-308
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• 2003

본 논문에서는 24GHz에서 동작하는 2단 저잡음 증폭기를 설계 및 제작하였다. 소자는 NEC사의 NE450284C HT-FET를 사용하였고, 양호한 잡음지수를 위한 정합회로 설계 시 좋지 않은 입력 정재 파비를 동시에 고려하여, 원하는 잡음지수와 입력 정재파비를 얻도록 설계하였다. 측정 결과 이득은 16.6dB, 입력 정재파비는 1.6, 그리고 출력 정재파비는 1.5를 넘지 않는 특성을 얻었다.

• 한국전자파학회논문지
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• 제27권12호
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• pp.1069-1074
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• 2016

본 논문에서는 TSMC 65 nm CMOS 공정를 이용하여 V-대역 이단 전력증폭기를 설계 및 제작하였다. 수동소자를 사용한 간단한 구조의 정합회로를 구성하였고, 입력과 출력 정합회로를 모두 집적하였다. Pre-distortion 기법을 통해 전력 이득을 보상해 줌으로써 전력증폭기의 선형성을 향상시켰다. 제작된 전력증폭기는 58.8 GHz의 동작 주파수와 1 V의 동작 전압에서 10.4 dB의 전력 이득, 9.7 dBm의 출력 전력 및 20.8 %의 효율 특성을 나타내었다.

• Journal of Power Electronics
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• 제11권6호
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• pp.779-786
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• 2011

This paper presents a soft switching converter to achieve the functions of zero voltage switching (ZVS) turn-on for the power switches and dc voltage step-up. Two circuit modules are connected in parallel in order to achieve load current sharing and to reduce the size of the transformer core. An active snubber is connected between two transformers in order to absorb the energy stored in the leakage and magnetizing inductances and to limit the voltage stresses across the switches. During the commutation stage of the two complementary switches, the output capacitance of the two switches and the leakage inductance of the transformers are resonant. Thus, the power switches can be turned on under ZVS. No output filter inductor is used in the proposed converter and the voltage stresses of the output diodes is clamped to the output voltage. The circuit configuration, the operation principles and the design considerations are presented. Finally, laboratory experiments with a 340W prototype, verifying the effectiveness of the proposed converter, are described.

• Transactions on Electrical and Electronic Materials
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• 제10권2호
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• pp.44-48
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• 2009

A simulation study of a 10-bit two-stage DAC was done by using a conventional current switch cell. The DAC adopts the segmented architecture in order to reduce the circuit complexity and the die area. The 10-bit CMOS DAC was designed in 2 blocks, a unary cell matrix for 6 MSBs and a binary weighted array for 4 LSBs, for fabrication in a 0.35-${\mu}m$ CMOS process. To cancel the accumulation of errors in each current cell, a symmetrical switching sequence is applied in the unary cell matrix for 6 MSBs. To ensure high-speed operation, a decoding circuit with one stage latch and a cascode current source were developed. Simulations show that the maximum power consumption of the 10-bit DAC is 74 mW with a sampling frequency of 100 MHz.

• Journal of Magnetics
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• 제20권3호
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• pp.322-329
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• 2015

This paper presents a new overlapped coilgun configuration to launch medium weight projectiles. The proposed configuration consists of a two-stage coilgun with overlapped coil covers with spacing between them. The theoretical operation of a multi-stage coilgun is introduced, and a transient simulation was conducted for projectile motion through the launcher by using a commercial transient finite element software, ANSOFT MAXWELL. The excitation circuit design for each coilgun is reported, and the results indicate that the overlapped configuration increased the exit velocity relative to a non-overlapped configuration. Different configurations in terms of the optimum length and switching time were attempted for the proposed structure, and all of these cases exhibited an increase in the exit velocity. The exit velocity tends to increase by 27.2% relative to that of a non-overlapped coilgun of the same length.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.694-700
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• 1998

A novel zero-voltage-transition (ZVT) isolated PWM boost converter for single stage power factor correction (PFC) is presented to improve the performance of the previously presented ZVT converter[8]. A simple auxiliary circuit which includes only one active switch provides zero-voltage-switching (ZVS) condition to all semiconductor devices. (Two active switches are required for the previous ZVT converter) This leads to reduced cost and simplified control circuit comparing to the previous ZVT converter. The ZVS is achieved for wide line and load ranges with minimum device voltage and current stresses. Operation principle, control strategy and features of the proposed converter are presented and verified by the experimental results from a 1.5 kW, 100 KHz laboratory prototype.

• 전력전자학회논문지
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• 제7권2호
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• pp.165-170
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• 2002

이단 전력변환에 따른 시스템 효율의 감소문제를 해결하기 위해서 배터리 구동 전자레인지를 위한 직렬 공진형 풀 브릿지 인버터 회로를 제안한다. 이 회로는 기존의 HVT(High Voltage Transformer) 방식과 비교해서 콤팩트 한 크기를 가지며 무게 또한 가볍다. 또한, 주파수 제어로 전자레인지의 출력단계를 조절할 수 있다. 본 논문에서는 회로 동작을 이해하기 위해서 동작원리를 자세히 설명하였다. 또한, 1[kW] 소비전력을 갖는 프롯타입 인버터 회로를 제작하고 시험을 통하여 동작을 확인하였다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.400-402
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• 2008

A new interleaved forward converter, adopting series-input parallel-output structure with a common transformer reset circuit, is proposed in this paper. Series-input structure distributes the voltage stress on switches, which makes it suitable for high input voltage application. Paralleling output stage with an interleaving technique enables the circuit handle large output current and reduces filter size. In addition, since two forward converters share one active-clamp circuit for the transformer reset, its primary structure is simplified. All these features make the proposed converter promising for high input voltage applications with high efficiency and simple structure.